Taming Corner Explosion In Complex Chips


There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

The Vital Role Of 1.6T Networking In Emerging Technology


Although warehouses filled with acres of buzzing server racks may not seem like the most likely places to find exciting new technology, data centers play a crucial role in the emerging technologies of tomorrow. Industry 4.0, artificial intelligence (AI), virtual reality (VR), metaverse, and Internet-of-Things (IoT) are all high-demand applications which rely on data centers to provide powerful ... » read more

Leveraging Chip Data To Improve Productivity


The semiconductor ecosystem is scrambling to use data more effectively in order to increase the productivity of design teams, improve yield in the fab, and ultimately increase reliability of systems in the field. Data collection, analysis, and utilization is at the center of all these efforts and more. Data can be collected at every point in the design-through-manufacturing flow and into the f... » read more

How To Make Chiplets A Viable Market


At the recent Chiplet Summit, there was a panel session on the last afternoon titled "How to Make Chiplets a Viable Market." The panel was moderated by Meta's Ravi Agarwal, and the panelists were (from left to right in the photo): Travis Lanier of Ventana Micro Systems...actually Travis couldn't make it and Ventana was represented by Charles, but I didn't catch his last name Clint Walk... » read more

Dealing With Performance Bottlenecks In SoCs


A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization


The implementation flow for semiconductor devices is all about optimizing for power, performance, area (PPA), or some combination of these attributes. The history of this flow in electronic design automation (EDA) tools is all about adding more automation, tightening iterative loops, and reducing the number of iterations. The goal is converging to the PPA targets faster while using fewer resour... » read more

Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster


Designers everywhere know that with the increasing complexity of integrated circuits (ICs), meeting tapeout schedules has become increasingly difficult. While there are often many reasons for missing tapeouts, one critical component is the significant amount of time needed to run the signoff layout verification cycle, which contributes to overall signoff process duration. Much of this schedule ... » read more

Make The Right Choices For Enhanced Security On RISC-V


Two things are certain to make their presence felt at Embedded World 2023: the growing presence of RISC-V and the importance of safety and security in any embedded system. The breadth of RISC-V applications is expanding rapidly from IoT, mobile devices, to high performance computing, automotive and more. Its adoption, along with RISC-V International memberships, is also expanding from start... » read more

Smart Energy Metering For A Greener Future


One of the key ways we will realize a sustainable future is to optimize—and essentially reduce—our energy usage. Optimization starts with understanding how much energy we consume every day. And to understand this, we must measure the power we consume in everyday applications. The smart meter is an important tool to help us transition to a “greener” use of energy. What is a smart ene... » read more

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking


Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows that require correct connectivity for valid results. The Calibre nmLVS Recon tool targets essential and relevant early-stage circuit verification pain points, such as electrical rule checking (ERC) ... » read more

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