Blog Review: May 12


Cadence's Claire Ying points to major changes in PCIe 6.0 as PAM4 signaling replaces NRZ to help double bandwidth, Forward Error Correction helps maintain data integrity, and various improvements are made to power consumption. Synopsys' Samantha Beaumont argues that automotive sensors are a major potential attack point and addresses some of the key areas of sensor vulnerability and the chall... » read more

Recommendations And Solutions For USB-C PD Chargers


The recent enhancements and technology advancements in the charger domain have made engineers face new challenges in their daily lives. Higher efficiency, smaller footprint with the same output power, or more power in the same footprint are among the key challenges in contemporary charger designs. In this whitepaper, Infineon provides engineers with an overview of different solutions in the USB... » read more

Study On High-Performance Computing Usage For Engineering Simulation


Simulation will play a critical role in the development of new market disrupting technology, from autonomous vehicles to 5G cellular networks, and the need for on-premises or cloud-based HPC resources to support those efforts is only going to increase. This white paper explores: How companies are using HPC-based simulation. The effect of the COVID-19 pandemic on HPC usage and adoptio... » read more

Accellera’s Functional Safety Group White Paper


"The objective of the Functional Safety Working Group is to standardize information for capturing and propagating the safety intent from the system down to the SoC / IP design and implementation including failure mode propagation, verification, validation, reliability and Safety Mechanisms. The safety intent standardization will support data exchange and traceability across different safety ana... » read more

Recalculating The Cost Of Test


The cost of test is rising. For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn't seem to be any single formula for determining it. In some cases, there isn't even a sense of urgency to finding out. Several significant changes are occurring that make any formula difficult to cal... » read more

Understanding Optical Inspection For CIS


The demand for smartphone cameras, video conferencing, surveillance and autonomous driving has fueled explosive growth of CMOS image sensor (CIS) manufacturing in the last decade. While CIS becomes an increasingly important element in the production of today’s consumer electronics, there are unique challenges in production that must be addressed. As pixel sizes shrink, we see an inverse relat... » read more

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy


You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Chip Monitoring And Test Collaborate


As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

Testing AiP Modules In High-Volume Production


Far-field and radiating near-field are two options for high-volume over-the-air (OTA) testing of antenna-in-package (AiP) modules with automated test equipment (ATE) [1]. In this article, we define an AiP device under test (DUT) and examine the measurement results from both methods. Creating an AiP evaluation vehicle Proper evaluation of an ATE OTA measurement setup requires an AiP module. Us... » read more

Testing Analog Circuits Becoming More Difficult


Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

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