How to determine appropriate electrostatic discharge robustness requirements.
Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric breakdown resulting from three primary event models:
No matter the cause, all ESD events can cause a metal melt, junction breakdown, or oxide failure. ESD can damage an electronic component at any stage of its production or use if not properly prevented. ESD events typically cause ICs to fail prematurely, or to operate at less-than-designed functionality, neither of which is good for market reputation!
How can I protect my ICs from ESD events?
Multiple protection schemes are used to avoid or mitigate ESD damage [1,2]. Designers must add proper ESD protection schemes on both the schematic (early in the design cycle) and layout. Checking for these ESD protection circuits before fabrication is essential for reliable design. ESD design rules are included in design rule manuals to verify the presence of appropriate ESD protection from a topological perspective.
Is ESD protection for 2.5D/3D ICs really any different from ESD protection for 2D ICs?
Yes and no. First, let’s look at 2.5/3D IC construction. 2.5D/3D ICs have evolved into an innovative solution for many design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the BGA substrate. In 3D ICs, dies are mounted on top of each other. Through-silicon vias (TSVs) are used for communication between dies and communication with the substrate.
Fig. 1: 2.5D versus 3D IC designs.
In 2D ICs, all pads act as IO interfaces that communicate with the outside world through the package pins. Because there are multiple dies in 2.5D and 3D integrations, some pads are used to communicate signals between dies through micro-bumps, TSVs, and the interposer, and don’t communicate with the outside world at all (figure 2). This key difference in 2.5D/3D ICs requires that we differentiate between those two categories of pads by classifying them as either external IOs that connect to the outside world or internal IOs that only connect within the 2.5/3D IC package.
Fig. 2: External IOs versus internal IOs.
Why is this important? Such classification is crucial to ESD protection because external IOs are connected to the package pins and face more ESD events than internal IOs [3]. Similar to 2D ICs, both external and internal IOs are affected by HBM and CDM ESD events. However, internal IOs will be affected less severely by these events. This difference means designers can use smaller ESD protection circuits for internal IOs, which in turn translates into significant saving in die area and cost without sacrificing any ESD robustness.
In short, the ESD protection circuit designs aren’t different, but how they are applied to a 2.5/3D IC matters a lot to the end result.
If the protection circuits are the same, what are the challenges for automating ESD verification in 2.5D/3D ICs?
There are a number of challenges to implementing automated ESD verification in 2.5D/3D ICs. Electronic design automation (EDA) tool suppliers must be able to provide a solution that resolves the issues summarized in the following points [4]:
So, is there an automated ESD verification methodology for 2.5D and 3D ICs?
A systematic methodology has been formulated to verify the ESD robustness of 2.5D and 3D ICs at the assembly level, die level, and complete 2.5D/3D IC design level [5], as shown in figure 3. This methodology requires the following elements: ESD constraints, assembly layout, die layouts, parasitic resistance rule decks, and layout vs. schematic (LVS) rule decks. At Siemens, we’ve implemented this methodology using the Calibre PERC reliability platform [6].
Fig. 3: ESD verification methodology.
The first stage extracts the relevant ESD data from the assembly layout required to capture the effect of interposers/interfaces. This stage consists of the following steps:
The second stage extracts the relevant ESD data from the die layouts. This process must be repeated for each die, because die can be designed on different technology nodes and manufactured using different foundries. These steps include:
The third stage performs ESD verification on the complete 2.5/3D IC design level by merging the data from the previous stages, running structural ESD checks on the complete design to report missing or incorrect ESD protection circuits, and computing total P2P for all the correct protection circuits to determine if they are sufficient.
How, exactly, does this methodology check for appropriate ESD protection schemes?
Layout netlists for the assembly level (i.e., interposer/interfaces) and all dies are available from the layout extraction performed in the assembly-level and die-level analyses, respectively. The complete 2.5D/3D IC netlist is generated by combining all of these netlists in one netlist, which enables structural ESD checks to be run at the complete 2.5D/3D IC design level.
There are three categories of protection schemes: ESD for external IOs, ESD for internal IOs, and ESD for supply. The purpose of all ESD checks is to identify missing/wrong/correct protection schemes based on a user-defined structure for each category. Table 1 lists the ESD checks that can be performed for each IO type versus the ESD protection scheme.
Table 1: ESD Protection Checks
One result that designers should take note of is the use of an external IO ESD circuit for an internal IO. Although that external IO protection scheme is a correct ESD protection method, it results in unnecessary ESD protection. Because internal IOs typically face ESD events less often than external IOs, they can usually be adequately protected by ESD devices that are smaller in size than those needed for external IOs, saving final product area.
For missing/wrong ESD protection schemes, problematic external IOs and internal IOs are reported as violations for which results can be debugged. For correct ESD protection schemes, relevant external and internal IOs are reported for information only to aid in debugging. In the case of correct ESD protection schemes, the routing is validated to check whether or not it can handle the ESD event by computing the total P2P parasitic resistance for every correct protection route and checking current density.
Does this methodology work in the real world?
We tested this verification methodology on a design with five die: four random-access memory (RAM) die and a controller die (figure 4). External and internal IOs were intentionally designed with missing, wrong, or correct ESD protection structures. The methodology correctly identified all expected violations, enabling designers to quickly identify and apply the correct fixes.
Fig. 4: Design layouts for the assembly of the five die (left) and one RAM die (right).
Can you sum it up for us?
From an ESD verification perspective, you should not treat 2.5D/3D ICs as a group of independent 2D ICs connected together. In these designs, ESD devices can span multiple die and must be combined for correct evaluation. You should also classify ESD events for the different IO types—internal IOs face fewer ESD events than external IOs, so identifying where these internal IOs are in the 2.5D/3D IC lets you place appropriate smaller ESD protection circuits to avoid wasting the chip area. While ensuring adequate ESD protection for a 2.5/3D IC contains many tasks that must be carefully managed, implementing an automated ESD verification methodology such as this one can make it much easier to ensure accurate and consistent ESD protection.
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