112G SerDes Modeling And Integration Considerations


The ever-increasing demand for compute power and data processing in accelerators, intelligence processing units (IPUs), GPUs, as well as training and inference SoCs is driving the adoption of 112G SerDes PHY IP solutions. Ensuring a reliable Ethernet link and efficient integration are the most essential requirements that designers need to meet. IBIS-AMI modeling can help predict SerDes link per... » read more

Imec’s Plan For Continued Scaling


At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world sinc... » read more

Improving Automotive Electronic Hardware With SAE J3168


By Theresa Duncan and Craig Hillman The race is on for fully autonomous vehicles. Industry giants like Tesla, Google, Uber and almost all major automotive companies are competing to deliver state-of-the-art self-driving vehicles. However, the development of new, cutting-edge technologies demands a similar wave of reliability, repairability and warranty standards that automotive manufactur... » read more

10X Faster Electromagnetic 3D Simulation


Virtual prototypes are essential to optimize the signal integrity performance of their high-performance electronics products. Today, engineering teams are pushing to get fast electromagnetic (EM) simulations of printed circuit boards (PCB) and 3D chip packages in just a few hours with the highest level of accuracy. The state of the art in EM simulation has come a long way: Back in 2000 it wa... » read more

Fast, Low-Power Inferencing


Power and performance are often thought of as opposing goals, opposite sides of the same coin if you will. A system can be run really fast, but it will burn a lot of power. Ease up on the accelerator and power consumption goes down, but so does performance. Optimizing for both power and performance is challenging. Inferencing algorithms for Convolutional Neural Networks (CNN) are compute int... » read more

What Designers Need to Know About Error Correction Code (ECC) In DDR Memories


As with any electronic system, errors in the memory subsystem are possible due to design failures/defects or electrical noise in any one of the components. These errors are classified as either hard-errors (caused by design failures) or soft-errors (caused by system noise or memory array bit flips due to alpha particles, etc.). To handle these memory errors during runtime, the memory subsyst... » read more

Functional Safety For Fail-Operational Systems


Functional safety issues have long been an important part of product development wherever machine operations that are potentially dangerous for humans are carried out unattended. However, in terms of electrical and electronic systems, the need has been limited to a few industries such as medical technology and aerospace. Apart from that, the functional safety concepts were only used for niche p... » read more

Attaching Fibers To Photonic Chips


Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs The third day was all about how to connect the incoming and outgoing fibers to the photonics chips. I will cov... » read more

Standard Benchmarks For AI Innovation


There is no standard measurement for machine learning performance today, meaning there is no single answer for how companies build a processor for ML across all use cases while balancing compute and memory constraints. For the longest time, every group would pick a definition and test to suit their own needs. This lack of common understanding of performance hinders customers' buying decis... » read more

Pushing The Envelope With HBM2E Memory


In September, Rambus announced the achievement of reaching 4 gigabits per second (Gbps) operation with our HBM2E memory interface. This milestone was demonstrated in silicon and required mastering substantial signal integrity and power integrity (SI/PI) challenges. The 4 Gbps mark represents a 20% rise from the previous maximum data rate of 3.2 Gbps for HBM2E. To date, the industry’s faste... » read more

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