Security For Android-Based Ecosystem With Mobile Storage IP


By Biswanath Tayenjam and Licinio Sousa Users are storing more sensitive data in flash memory on their mobile applications such as digital cameras, smart phones and tablets. Because of this reason, the Joint Electron Device Engineering Council (JEDEC) have developed two storage interface standards using inline encryption to secure data: embedded Multimedia Controller (eMMC) and Universal Fla... » read more

Optimizing The Data Center With PCI Express 4.0


PCI Express (Peripheral Component Interconnect Express), also known as PCIe, is a high-speed serial computer expansion bus standard designed to replace older PCI, PCI-X and AGP bus standards. Officially launched in 2003, PCIe was rapidly adopted by chip, system and software designers and emerged as the dominant interface standard for connecting peripherals to the CPU. Modern CPUs rely on the... » read more

Co-Modeling Takes Emulation To The Next Level: System-Of-Systems


As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Today�... » read more

SoC Electromagnetic Crosstalk: From A Tool Perspective


Most commercial electromagnetic (EM) solvers are limited by the size of the design that they can handle, or they may take a very large amount of time or memory to perform the task. These capacity, memory or runtime constraints often lead to dropping important details about the design and the surrounding environment, which in many cases can mask the effects of EM crosstalk, or can lead to the wr... » read more

Getting Power Management Right


Getting power management right in the era of heterogeneous SoCs is a multi-pronged effort, there's no getting around it. Engineering teams daily try to squeeze more and more power from their designs, which many times includes adding human resources and expertise to the project. Take an example where a design team leader gets the mandate to include high level synthesis in the design metho... » read more

An Incremental Approach To Reusing Automated Tests From IPs To SoCs


Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

Electromagnetic (EM) Crosstalk Analysis: Unlocking the Mystery


Ignoring electromagnetic crosstalk is highly risky and can cause significant time-to-market delays as well significant cost over runs. Most current SoC design flows fundamentally ignore inductance and EM effects, and the term “EM crosstalk analysis” may sound Greek to them. This short article provides a quick overview of the basic steps involved in doing EM crosstalk analysis as part of an ... » read more

The 5G Design Dilemma


Nothing says low power and high performance like an emerging wireless standard that promises to increase link bandwidth, latency, and overall capacity by orders of magnitude while also reducing power. That emerging standard, of course, is 5G. With the number of devices that are projected to use 5G, it’s no surprise that 5G is a strategic initiative for many companies. This explains why des... » read more

Software Framework Requirements For Embedded Vision


Deep learning techniques such as convolutional neural networks (CNN) have significantly increased the accuracy—and therefore the adoption rate—of embedded vision for embedded systems. Starting with AlexNet’s win in the 2012 ImageNet Large Scale Visual Recognition Challenge (ILSVRC), deep learning has changed the market by drastically reducing the error rates for image classification and d... » read more

The Promises And Challenges Of 7nm


Despite a waning Moore’s Law and the increasing costs of advanced process nodes, the semiconductor industry is steadily approaching 7 nanometers (nm). The demand for 7nm is driving expected initial tape-outs from fabs by the end of 2017, with initial volumes beginning in 2018 and ramping up by 2019. Silicon fabbed on 7nm nodes will offer a number of benefits for chipmakers, including lower po... » read more

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