category: Power Source

category: IoT, Security & Automotive

Early Power Budgeting for Live Applications
By Meni Jayaswal - 16 Jun, 2015 - Comments: 0

Today, power and energy efficiency are at the forefront of SoC design. Functional activity has a first-order impact on power. Increasing functional integration requires a comprehensive analysis of power consumption across complex modes of operation. Power inefficiency in any one mode can have a significant impact on the competitiveness of a product or time to market. So designers are looking fo... » read more

How Switching Activity Impacts A Design’s Power And Reliability
By Chris Ortiz - 14 May, 2015 - Comments: 0

Electronics continue to gain presence in both familiar and unfamiliar areas of our lives. Electronics is a common thread among the cars we drive, the computers we use, the mobile phones and wearable devices that we rely on. We appreciate the information and convenience that Fitbits and other products such as coffee makers, credit cards and building security cards provide us. And we are beginni... » read more

UPF-Driven RTL Power Budgeting For Energy-Efficient Designs
By Arti Dwivedi - 09 Apr, 2015 - Comments: 1

Energy efficiency of devices has become more critical than ever, with shrinking geometries and increased performance requirements of SoCs in applications ranging from mobile, storage, automotive to processors. Power management, therefore, becomes an important part of IP and SoC design methodology. While power management is critical in all design stages, an important aspect of this methodolog... » read more

Package Modeling Needs For A Robust IC Power Integrity Sign-Off
By Chris Ortiz - 12 Mar, 2015 - Comments: 0

Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in t... » read more

Low-Power Design Is More Than Just Minimizing Power
By Muhammad Zakir - 12 Feb, 2015 - Comments: 0

Engineers are accustomed to making tradeoffs when designing products — faster and more power-hungry, or slower and lower-power; expensive and durable, or cheap and disposable; and so on. The ongoing list of tradeoffs and subsequent choices that need to be made can sometimes appear quite daunting. This blog discusses how the design of electronic systems in the context of power has expanded bey... » read more

IP Design Essentials For Reliability And SoC Integration
By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

Smart Early ASIC Design Prototyping And Analysis
By Sankar Ramachandran - 04 Dec, 2014 - Comments: 0

The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task. With increasing competition in the market, delivering chips on time with 'first silico... » read more

IP Design Essentials For Power Integrity
By Annapoorna Krishnaswamy - 06 Nov, 2014 - Comments: 0

Smart connectivity is the new mantra of today – the ability to connect to anything, anywhere and at any time. With such technology enablement, low power is not a choice but an expectation. Whether it is a connected device, or a system that is part of the infrastructure, they are driven to integrate various functionality such as high speed computing, high-speed memory, memory interfaces, radio... » read more

Ubiquitous Trend In Design for Power (DFP) For IP And SoCs
By Vic Kulkarni - 09 Oct, 2014 - Comments: 0

Semiconductor design engineers must meet power specification thresholds, or power budgets, that are dictated by the electronic system vendors to whom they sell their products. Analyzing and reducing power across the board in all market segments has become a key requirement and a differentiator, especially over last 8 to 10 years for IP and IP-based SoC designers. Many products live and die due ... » read more

Can RTL Clock Power Be Accurate Enough For Sub-20nm Multi-GHz Designs?
By Preeti Gupta - 11 Sep, 2014 - Comments: 0

The Register Transfer Language (RTL) has increasingly been adopted to enable early and high-impact power decisions. As a cycle-accurate hardware abstraction, RTL is expected to deliver reasonable power accuracy. Clocks are particularly important to analyze and optimize for power. They switch the most and drive the highest loads. Clock gating is an effective power reduction technique that shuts ... » read more

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