Package Modeling Needs For A Robust IC Power Integrity Sign-Off

Power integrity for today’s designs requires accurate modeling of voltage variation across die and efficient coupling between chip/package layouts in a unified platform.


Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in the chip that adversely affects the operation of the SoC.

Power integrity analysis ensures that the voltage seen by the individual transistor is as robust as possible across all operating modes of the chip. However, the increasing sophistication of the SoCs and the underlying semiconductor processing technologies have made analysis more complex and demanding. Inclusion of package and PCB parasitics in the SoC power integrity analysis has become a standard practice, yet the package and PCB models used for analyses and sign-off tend to lack several of the required elements.

Due to increasing size of an SoC, variation in switching current, and the parasitic profile across the chip, the individual connections between the SoC and the package at the C4 bump level need to be as granular as possible. The traditional approach of grouping the bumps either into a ‘lumped’ connection or as 4X4 or 6×6 groups does not provide the granularity required for accurate time-domain simulation. In addition, the parasitics associated with the various power and ground networks (or domains) should be kept separate, and allow all the degrees of freedom to model any current return path using the package parasitic elements.

These aspects are required for simulating each individual power or ground domain to achieve a more realistic voltage gradient across the die. During the SoC power integrity analysis step it is important to bring in accurate and appropriate models of the package into the chip-level simulation.

Accuracy of package modeling for IC design
Use of 3D Finite Element Method engine for package extraction not only provides the accuracy, but also handles areas not well covered by the reference planes, and planar geometries with slits and perforations. Accurate package extractions with tight integration to the chip power integrity analysis will help provide valuable feedback to the package design in the early stages where significant routing changes are most easily implemented.

When the bumps are grouped together to form the connection between the chip and the package model, the entire chip capacitance is seen as a single total value by the package. The parts of the SoC that are not switching end up providing their capacitances to the active portions of the SoC due to artificial shorting. Hence, the noisy sections of the chip will appear to have more capacitance at their disposal to provide charge for the high frequency noise, whereas the quiet section will appear to have more charge moving on/off its local capacitance. This distorts the voltage variation across the die by uniformly reducing the voltage drop across the chip. The only variation seen is the voltage drop from power grid in individual sections of the chip.

With a distributed package model both the chip network and package network are providing impedance across the die resulting in a more realistic voltage gradient. Bumps at the periphery of the chip will have higher impedance and if the switching current is higher there, those areas will have higher drop at the bumps, while the center area of the chip with lower impedance will see lower drop at the bumps. This variation in the bump level voltage drop is more realistic and consistent with what is seen in reality.

Fig. 1. Voltage drop distribution of a chip for three types of analyses: a) without package (green), b) lumped package (blue), and c) distributed package (red).

Typically there are two types of package models used to represent the parasitics of the package structures. One type is the terminal-based RLCK model. The other is a port based S-parameter model. An RLCK model is a more physical model and behaves in a more intuitive manner, whereas an S-parameter model while providing a more broadband response is less suitable for power integrity analysis.

With an RLCK model, the noise on the power and ground networks can be analyzed separately. This allows for quick determination if supply noise is on the power network, ground network or both. With an S-parameter it is not possible to separate the parasitic behavior of the power network from that of the ground (reference) network. Also with the port based S-parameter model, a given port’s return current is locked into the reference node of the port. This fixed symmetry in currents between the port nodes is typically not correct and limits the resolution (minimum number of bumps used for the return current) that an S-parameter can provide without providing a pessimistically high impedance.

RLCK models typically have less bandwidth than S-parameter models, but a high bandwidth is not needed to predict accurate voltage noise at the instance level. This becomes more intuitive when recognizing that at the instance level, the impedance becomes dominated by the chip after a few hundred MHz. (See Fig. 2.)

Fig. 2. A plot of the supply impedance as seen from the PG pins of a given on-chip instance. The low frequency (<1MHz), impedance is due to resistance of chip and package. At about 100MHz the package inductance begins to dominate. At high frequencies (>1GHz), the on-die capacitance dominates the supply impedance.

The need for Unified Chip-Package Analyses
Today’s SoCs have a large number of distinct power and ground supplies, each with hundreds of C4 bumps. Additionally, a large number of possible activities can take place changing the current profile significantly across the chip and over time. With so much variation in power density across the die it is important to be able to perform power integrity analysis over a larger number of conditions without increasing the design cycle. Also, it is becoming more critical that the chip and package must be analyzed for power integrity in the context of each other and their unique conditions. The most natural way to improve the efficiency for chip-package co-analysis is to easily bring both the package layout and the chip layouts into the same simulation platform.

This unified approach eliminates the tedious and error-prone process of connecting an externally created package model to a chip and performing voltage drop analysis, taking the impact package has on the chip. It also enables a package designer to understand the impact of the chip on the package.

This calls for a GUI-based setup for the co-layout environment, which is easy, and with clear messaging should any issues arises during setup.

The ability to add SPICE models using the GUI for package decaps, or include a model for the board-level PDN, helps with what-if analysis and simulations for longer time scales respectively.

A tcl-based scripting language interface eases the setup and provides an efficient way to share flow information with others. It simplifies batch-mode multi-run analysis where no real-time input is needed to change setups and run analysis.

Beyond power integrity
Having both chip and package design data available provides the ability to predict EMI effects for the large current swings related to on-chip high-frequency activity. Also, knowledge of a chip’s power variation with respect to temperature allows for more accurate thermal analysis—both with regard to the heat dissipation from the external environment, as well as feeding that information back into the chip for a more precise thermal profile.

It will continue to be the case that with such complex distributions of power density and supply networks, both the package and the chip will need to be analyzed in the context of each other for a large number of conditions. Having the package and chip layouts associated with each other in the same simulation platform will help improve efficiency and enable chip-package convergence.

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