How Switching Activity Impacts A Design’s Power And Reliability

Designing for low-power efficiency requires a thorough understanding of switching scenarios and their effects.


Electronics continue to gain presence in both familiar and unfamiliar areas of our lives. Electronics is a common thread among the cars we drive, the computers we use, the mobile phones and wearable devices that we rely on.
We appreciate the information and convenience that Fitbits and other products such as coffee makers, credit cards and building security cards provide us. And we are beginning to enjoy the feature-rich small devices that are traditionally considered as apparel (think of Dick Tracy’s watch).

All electronic devices need power to operate, and when power runs out it has to be replenished. Our lives have evolved around these electronic devices so much that being without one of them, even on a temporary basis, is seen as a hardship. As a consumer of a smart phone, the battery life or the ability to simultaneously run maximum number of applications trump the need for higher performance or rich feature set. These sentiments are driving designers to put a lot of thoughts on power when designing a device. The device must handle any task issued by the user with as little power and/or power noise as possible. While the passive Power Distribution Network (PDN) plays an important part in keeping the voltage supplied to all the devices stable, it is the active switching of the devices themselves that mainly determine the total power consumed, and identify the parts of a design with potential reliability issues leading to failure over time.

Designing for low power efficiency requires a thorough understanding of switching scenarios and their impact. Switching not only refers to the signal and logic activity on the chip, but also to switching different power domains on and off. By dynamically switching the power to certain blocks on and off, depending on the demand, the overall power consumption is reduced and the battery life of the design is extended. This reduction in power due to more efficient switching also reduces the thermal imprint, thereby improving the reliability of the device. With the demand for increased functionality and battery life, and reduced form factors, the use of 2.5D/3D packaging technology is very common in mobile devices. This places chips in closer proximity to each other resulting in reduced thermal dissipation. Efficient switching for these devices improves reliability and reduces electromigration, and the reduction in power improves usability of the overall product by extending its battery life.

Figure 1. Diagram of heat conduction and dissipation for a 3D-IC system.

Switching and associated thermal issues are also a concern for high power chips found in the compute or networking space. For these systems, performance is more important than low power and the chips used have fast switching times to maximize their performance. However, these silicon technologies also have low channel resistance, which means high leakage current. This leakage increases at an exponential rate as temperature increases. If not designed carefully, the high switching activity in different parts of the core logic can increase the temperature to a point where leakage becomes a dominant component of power consumption or heat generation. If unchecked, it is possible for the leakage and temperature of the chip to increase at a rapid rate until the chip burns out in what’s called a thermal runaway. However, with efficient switching and accurate thermal analysis the probability for thermal runaway can be minimized during design.

Power noise is big concern in the compute/networking space. While it is critical to design a good PDN that supplies stable power to the chip, the managing the switching on the chip can be just as critical. The activity on these chips is typically in the multi-GHz range. Therefore all the charge consumed by the logic will be coming from capacitance on the die since the package impedance will be too high to supply enough charge over these switching times. The package is able to supply a good amount of current at lower frequencies. If care is taken to spread out the switching times of the logic on the die, so not all transistors are switching right after the clock edge, the net charge on the chip can remain fairly constant with little associated power noise. Determining how well the switching times are evenly spread can only be answered through careful transient simulation that includes chip and package in the analysis.

Figure 2. Switching activity and accurate chip modeling enable power and signal integrity aware system design.

In an automotive application, the switching activity can cause issues for power integrity as well as electromagnetic interference (EMI). If the current consumption at the target frequency is high, it leads to large EMI radiation. The planar structures of the conductors on a package or board can form an efficient radiator if excited at the proper frequency. Simulation is required to predict the electromagnetic compatibility of a part for a system. A key feature of any such simulation will be the ability to accurately account for the current and voltage activity throughout the package and board due to the operation of the chip.

Accounting for the switching activity of the chips allows system design to be intelligent, focused and effective in suppressing noise of all types and conserving power.