category: Perfecting The Process

category: IoT, Security & Automotive

The Next Technology Frontier In MEMS Gyroscopes
By Hideyuki Maekoba - 24 Feb, 2020 - Comments: 0

In MEMS technology development, it is always exciting to see the next technology frontier, the border of the known and the unknown. Talent and hard work (along with ingenuity) can move this frontier and enrich all of us. We respect the efforts of MEMS innovators, who have developed original and creative ideas by building upon past knowledge and wisdom and have integrated this knowledge across m... » read more

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance
By Taeyon (TY) Oh - 03 Feb, 2020 - Comments: 0

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design. Fig. 1 (a) DRAM Memory Cell, (b) GI... » read more

An Introduction To Semiconductor Process Modeling
By Jeonghoon (James) Kim - 20 Dec, 2019 - Comments: 0

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog will discuss an efficient technique to develop new process steps faster, with much less effort. Basic concept The easiest way to predict a process result is to model its b... » read more

A Study Of Next-Generation CFET Process Integration Options
By Benjamin Vincent - 21 Nov, 2019 - Comments: 0

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process m... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations
By Jacky Huang - 25 Sep, 2019 - Comments: 0

By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Advanced Patterning Techniques For 3D NAND Devices
By Yu De Chen - 15 Aug, 2019 - Comments: 0

By Yu De Chen and Jacky Huang Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At th... » read more

Controlling Variability Using Semiconductor Process Window Optimization
By Benjamin Vincent - 01 Jul, 2019 - Comments: 0

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wa... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing
By Pradeep Nanja - 23 May, 2019 - Comments: 0

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

Connecting Wafer-Level Parasitic Extraction And Netlisting
By Michael Hargrove - 18 Apr, 2019 - Comments: 0

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In thi... » read more

Improving SAQP Patterning Yield Using Virtual Fabrication And Advanced Process Control
By Benjamin Vincent - 25 Mar, 2019 - Comments: 0

Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ul... » read more

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