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Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)

Understanding the benefits and challenges of a new, next-generation semiconductor architecture

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In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we reviewed the use of different starting substrates (Si bulk, SOI, DSOI) and their specific challenges and opportunities with respect to CFET fabrication. We only considered Fin (or Nanowire)-based transistor structures in our prior study.

In collaboration with imec, we have now extended our earlier benchmark study to review a new design comprised of horizontal nanosheet transistors. This new CFET design is formed by using two stacks (one for n- and one for p-transistors) of two Nanosheets, processed one on top of the other. Figure 1 depicts the geometrical evolution from a Nanowire-On-Fin CFET to a Nanosheet-On-Nanosheet CFET design.


Fig 1: Geometrical CFET evolution from a 2 Nanowires-On- 2 Fins architecture to 2 Nanosheets-On- 2 Nanosheets architecture (NW: Nanowire, NS: Nanosheet, S: Source, D: Drain)

Benefits of New CFET Architecture
This new CFET architecture has two key benefits, highlighted in a recent paper published in the Journal of the Electron Devices Society [3]:

  • The new design allows relaxation of the spacing between the p- and n- transistors. It also eliminates unexpected shorts between the top and the bottom device, which is a key potential failure experienced in Fin architectures.
  • Lithography and patterning variability have a lower impact on electrical performance in Nanosheet-based CFET designs compared to Nanowire-based designs. In our study, we reviewed variations in both p- and n-FET performance using SEMulator3D’s Device Analysis (transistor modeling) functions. We discovered that the Nanosheet option exhibited much tighter control of electrical performance than the Nanowire option.

Modeling Process Challenges of Nanosheets in a CFET Design
The CFET Nanosheet-On-Nanosheet architecture presents one key technical challenge during Replacement Metal Gate (RMG) process integration. Specifically, during the metal recess step, metal must remain on the two bottom nanosheets while it is being completely removed both on and in-between the two top nanosheets. In order to assess the feasibility of this process, we used the SEMulator3D Process Window Optimization (PWO) module [4] to determine process and process window requirements. Five process parameters were considered in our PWO study:

  • SOC recess depth and isotropy
  • Metal recess depth and isotropy, and
  • SOC consumption during the metal recess step

One thousand (1,000) virtual wafer runs were executed with different distributions provided for each of the parameters. We used a nominal value, standard deviation and search space range for each parameter listed earlier. The PWO module calculated the process window required to ensure that the RMG integration flow was successful. The results (see Figure 2) indicated that:

  • Both SOC and metal recess must be fully isotopic
  • 90% selectivity of SOC is required during the metal recess (SOC etch rate = 0.1 * metal etch rate)
  • SOC and metal recess depth standard deviations must not be greater than 0.7nm (for 144 and 20nm recess targets, respectively)


Fig 2: Top – details on the distribution details for the five parameters considered in the 1000 run virtual DOE ; Bottom – SEMulator3D Process Window Optimization interface showing target and standard deviation values for each of the five parameters studied to reach a 99.8% predictive in-spec percentage target.

Conclusion
In conclusion, prior to Si wafer processing or tapeout, virtual processing allowed us to:

  • Identify a promising new design architecture for CFET
  • Quantitatively highlight the benefit of our new design in comparison to earlier designs
  • Determine the process and process windows required to successfully implement a new CFET design and integration flow

Virtual fabrication is a very attractive methodology for technology pathfinding development. It supports a greater number of technology and process experiments than is possible using wafer-based experimentation, with a much faster turnaround time and lower cost.

References

[1]https://www.coventor.com/blog/a-study-of-next-generation-cfet-process-integration-options/
[2] https://www.imec-int.com/en/articles/imec-presents-complementary-fet-cfet-as-scaling-contender-for-nodes-beyond-n3
[3] https://www.coventor.com/paper/benchmark-study-complementary-field-effect-transistor-cfet-process-integration-options-virtual-fabrication/
[4] https://www.coventor.com/blog/control-variability-semi-process-window-optimization/



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