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Cybersecurity Through Hardware-Based Threat Detection And Mitigation


SoC design teams fill a mission-critical role in ensuring cyber-physical safety and security for electrical and electronic systems that are connected to the internet. The requirements and tools available to achieve this goal are ever-shifting, but we can be fairly sure that traditional software-only security measures are unlikely to be sufficient; a new class of hardware-level monitoring is als... » read more

Automate Memory Test Through A Shared Bus Interface


The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Enabling Silicon Lifecycle Solutions


The concepts of product lifecycle management (PLM) should be familiar, although the semiconductor industry has yet to adopt a system for managing the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. Now, a combination of business and technical pressures is bringing PLM capabil... » read more

Simplify DFT For Advanced SoCs


The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

High-Quality Test And Embedded Analytics Are Vital For Secure SoCs


Applications like as smart cards and devices used in the defense industry require security to ensure that sensitive data is inaccessible to outside agents. This used to be a niche requirement met through custom solutions. However, now that automotive and cyber-physical systems are proliferating, the requirements around secure test and monitoring are becoming mainstream. The current best strateg... » read more

Success Stories For Packetized Scan Data


Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The calculation of whether (or when) to adopt new technology includes consideration of the pressures of DFT today—design complexity, the lack of flexibility in hardwiring scan channels, the proliferat... » read more

Novel Reversible Chain Diagnosis Improves Resolution


Yield ramp for ICs designed on advanced process technologies faces new challenges because of the very complicated silicon defect types and defect distribution. Yield ramp and yield improvement are not just about profitability and time-to-market, but also have a role in today’s electronics supply chain crisis. That means yield ramp affects not just the IC maker, but the global economy. Ever... » read more

Packetized Test At The International Test Conference 2021


At this year’s International Test Conference (October 10-15, 2021), Siemens Digital Industries Software is showcasing IC test and lifecycle management technologies that address the key scaling challenges facing the semiconductor industry now and in the future. The two main topics from Tessent at ITC are: The rapid adoption of packetized test strategies to address design and system... » read more

The Era Of Packetized Scan Test Has Arrived


For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

Better Optimization For Many-Core AI Chips


The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

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