category: A System Perspective

category: IoT, Security & Automotive

Balancing Flexibility And Quality In SRAM Verification
By Elven Huang - 30 Jan, 2020 - Comments: 0

Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

Cloud Characterization
By WeiLii Tan - 19 Dec, 2019 - Comments: 0

Library characterization is a compute-intensive task that takes days to weeks to complete. Runtimes for library characterization are increasing due to larger library sizes, higher number of operating conditions to characterize, as well as the need for statistical variation modeling in libraries at 22/20nm and smaller process nodes. Cloud platforms offer a way to accelerate library characterizat... » read more

A Reliable I/O Ring For A Reliable SoC
By Abdellah Bakhali - 26 Nov, 2019 - Comments: 0

What is an input/output (I/O) ring, and why should I care about it? If you’re a system-on-chip (SoC) designer, you had better know the answer to that question. SoCs are the darlings of the semiconductor industry—they combine all the typical functionality of a computer (central processing unit (CPU), memory, input/output (I/O) ports, and storage) on a single chip. They’re particularly popu... » read more

5G Needs Cohesive Pre- And Post-Silicon Verification
By Jean-Marie Brunet - 24 Oct, 2019 - Comments: 1

While 5G doesn’t start from a clean slate, it does make significant changes to the 4G architecture. These changes mean that the ecosystem from chips to operators is evolving, giving opportunities to more companies to engage in this growing market. Realignment in fronthaul, midhaul and backhaul In particular, the radio access network (RAN) has been redefined as Cloud RAN (sometimes called ... » read more

Fast-Track Your Early SoC Design Exploration And Verification
By Nermeen Hossam - 26 Sep, 2019 - Comments: 0

By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster
By Wael elManhawy - 22 Aug, 2019 - Comments: 0

By Wael ElManhawy and Joe Kwan A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a com... » read more

Taking EDA To The Cloud
By Omar El-Sewefy - 25 Jul, 2019 - Comments: 0

By now, virtually everyone knows about the “cloud”—that amorphous delivery of computing services over the Internet. Servers, storage, databases, networking, software, analytics, intelligence, and more are all on offer. Clouds may be private and limited to a single organization (enterprise clouds), be available to many organizations (public cloud), or a combination of both (hybrid cloud). ... » read more

Providing An AI Accelerator Ecosystem
By David Burnette - 27 Jun, 2019 - Comments: 0

A key design area for AI systems is the creation of Machine Learning (ML) algorithms that can be accelerated in hardware to meet power and performance goals. Teams designing these algorithms find out quickly that a traditional RTL design flow will no longer work if they want to meet their delivery schedules. The algorithms are often subject to frequent changes, the performance requirements may ... » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools
By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability
By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

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