Deconstructing Deep Learning


I discuss AI and deep learning a lot these days. The discussion usually comes back to “what is a deep learning chip?” These devices are basically hardware implementations of neural networks. While neural nets have been around for a while, what’s new is the performance advanced semiconductor technology brings to the party. Applications that function in real time are now possible. But wh... » read more

Making Sense Of Safety Standards


If you’re involved in the design or verification of safety-critical electronics, you’ve probably heard about some of the standards that apply to such development projects. If not, then you’re probably puzzled when you read about TÜV SÜD certifying that an EDA tool satisfies functional safety standards ISO 26262 (TCL3/ASIL D), IEC 61508 (T2/SIL 3) and EN 50128 (T2/SIL 3). The industry ha... » read more

AI And Machine Learning Drive New SoC Verification Choices


I have previously written about the choices that design teams have when choosing specific verification engines—virtual, formal, simulation, emulation, FPGA and actual silicon. As a new class of SoC is emerging for machine learning and artificial intelligence with complexities previously unheard of, they further deepen the challenge of choosing the right tool for the job. Even the choice betwe... » read more

DAC’s Passageway To Design Infrastructure


This year's Design Automation Conference will include an "alley" on the exhibit floor, but it won't be a dark, narrow passageway we think of when we hear "alley." Instead, the new Design Infrastructure Alley will be a well-illuminated tribute to the design technology infrastructure, a fundamental element for the creation and design of complex electronic systems and components. The Design Inf... » read more

Raising SoC Development Productivity With Portable Stimulus


The semiconductor industry has achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to re... » read more

Formal In The Spotlight


Who doesn’t like a great family picture during the festive season? Of course, those occasions call for reasonably elegant attire. When in the spotlight, most people like to get somewhat more formal. It seems that in the semiconductor world, it’s the reverse. As formal verification transitioned from a niche technology to mainstream over the past few years, formal verification engineers an... » read more

3D Extraction Necessities For 5nm And Below


For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more impo... » read more

It Takes A Village… To Develop And Verify SoCs


In my last blog post from 2017, “Design Chains Will Drive The Top 5 EDA Trends In 2018,” I had pointed to the importance of ecosystems for electronics development in general. From an EDA perspective, it also takes a village to shepherd the actual chip development with its complex verification and software development tasks. And the types of partnerships often depend on the application domai... » read more

Analyzing Data Differently


Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonde... » read more

In Case You Missed It


We recently held two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic p... » read more

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