category: Blogs – SLD

category: IoT, Security & Automotive

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools
By Roberto Piacentini Filho - 25 Jul, 2024 - Comments: 0

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and maintaining good reputations throughout their lifetimes. Unfortunately, many SoC teams attempt to use existing tools like Git for these essential tasks, even though they are unsuitable and inconv... » read more

Debugging SystemVerilog Constraint Randomization: A Comprehensive Guide
By Rich Chang - 25 Jul, 2024 - Comments: 0

SystemVerilog constraint randomization is a powerful methodology for generating realistic and diverse test scenarios in the realm of hardware design verification. However, like any complex methodology, it can sometimes be challenging to debug when an unexpected issue arises. In this article, we will explore common debug techniques and strategies to help you effectively troubleshoot your SystemV... » read more

Optimizing Interconnect Topologies For Automotive ADAS Applications
By Ashley Stevens - 25 Jul, 2024 - Comments: 0

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators... » read more

Language’s Role In Embodied Agents
By Ben Gomes - 27 Jun, 2024 - Comments: 0

Large Language Models (LLMs) and models cross-trained on natural language are a major growth area for edge applications of neural networks and Artificial Intelligence (AI). Within the spectrum of applications, embodied agents stand out as a major developing focal point for this AI. This article will address developments in this space and how the application of language-trained models improves t... » read more

RISC-V Verification: From Simulation To Formal
By Ashish Darbari - 27 Jun, 2024 - Comments: 0

Axiomise's Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design and how formal verification can help with bug hunting for corner-case bugs and exhaustive proofs of bug absence. » read more

Navigating The Future Of EDA
By Anika Sunda - 27 Jun, 2024 - Comments: 0

The landscape of electronic design automation (EDA) is undergoing a monumental transformation. The catalysts? Artificial Intelligence (AI) and Machine Learning (ML). These technological marvels are not just reshaping how we approach design and verification in electronics; they are redefining the possibilities within the field. Our latest podcast episode delved deep into this topic, uncovering t... » read more

The Fundamentals Of Software Testing
By Jonathon Wright - 27 Jun, 2024 - Comments: 0

Recently, I had a conversation with Paul Gerrard, the internationally renowned, award-winning software engineering consultant, author, and coach. We discussed the fact that testing is at the heart of software development. Obviously, as testers, we spend all day testing and thinking about testing. But developers test every line of code they write. Sometimes, users test. In fact, the all-perva... » read more

Streamlining SoC Design With Advanced IP And Integration Solutions
By Andy Nightingale - 27 Jun, 2024 - Comments: 0

As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The emphasis on physical awareness across solutions significantly reduces the iterative cycles of NoC placement and routing. By ensuring low latency and high efficiency, these advanced integration solution... » read more

Enabling 2.5D/3D Multi-Die Package
By Kenneth Larsen - 27 Jun, 2024 - Comments: 1

In the rapidly evolving world of ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of IC design innovation but also an increased complexity in coordination and integration. At the forefront of this technolo... » read more

Ensuring Your Power And Ground Nets Are Correctly Connected
By Terry Meeks - 03 Jun, 2024 - Comments: 0

In most chip designs, the power and ground nets are likely your largest and most important nets. If any devices are not properly connected, then you cannot expect them to function as expected. Amongst the many problems that can occur to power and ground involves the connections to the well areas of your design that power all the bulk connections to your devices. Well regions connectivity is oft... » read more

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