Chiplets Add New Power Issues

By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

Physics Simulation With Graph Neural Networks Targeting Mobile

By Máté Stodulka - 13 Mar, 2025 - Comments: 0

By Máté Stodulka and Tomas Zilhao Borges The demand for immersive, realistic graphics in mobile gaming and AR or VR is pushing the limits of mobile hardware. Achieving lifelike simulations of fluids, cloth, and other materials historically requires intensive mathematical computations. While these traditional methods yield highly accurate results, they have been too resource-heavy to run re... » read more

No Fooling With Voxel Pooling

By Steve Roddy - 13 Mar, 2025 - Comments: 0

A variety of new and complicated transformer models have emerged in the past 18 to 24 months as new “must have” networks in advanced automotive use cases. These novel architectures often introduce new network operators or novel ways of combining tensors – often from different types of sensors – in ways to enhance detection and recognition of objects in L3 / L4 / L5 ADAS and autonomous d... » read more

Integrating Data From Design, Manufacturing, And The Field

By Adam Kovac - 13 Mar, 2025 - Comments: 0

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as dimensions become smaller, and as more features are added into devices — especially with heterogeneous assemblies of chiplets running some type of AI — the potential for thermally induced structur... » read more

New Innovative Way To Functionally Verify Heterogeneous 2D/3D Package Connectivity

By Siemens EDA - 12 Mar, 2025 - Comments: 0

Historically, IC package design has been a relatively simple task which allowed the die bumps to be fanned out to a geometry suitable for connecting to a printed circuit board. The package netlist was often captured by the package designer, typically using Excel to manually assign net names to the desired die bumps and BGA balls to achieve the intended connection. Modern package and interpos... » read more

Silicon Reimagined: New Foundations For The Age of AI

By Arm - 12 Mar, 2025 - Comments: 0

The semiconductor industry is undergoing a pivotal transformation driven by the rise of artificial intelligence (AI) and the slowing of traditional Moore’s Law scaling. In this comprehensive 42 page report, several key trends shaping the industry’s future are highlighted. The push toward more specialized architectures tailored for specific workloads, particularly in AI. The critic... » read more

Application Of External CFD Modeling In Data Center Design

By Cadence - 12 Mar, 2025 - Comments: 0

Rising IT densities and AI workloads demand smarter heat management and equipment placement. This paper "Application of External CFD Modeling in Data Center Design" explores how external computational fluid dynamics (CFD) modeling provides crucial insights by resolving airflow patterns around buildings. Why Choose External CFD Modeling? Recommended by The Green Grid, it helps predict: ... » read more

Unlocking Generative AI On The Edge Across The Semiconductor Value Chain

By Expedera - 12 Mar, 2025 - Comments: 0

In the second of a three-part series, Expedera, in conjunction with the Global Semiconductor Alliance’s Emerging Technologies (EmTech) group, explores “Unlocking Generative AI on the Edge across the Semiconductor Value Chain”. Included in this white paper is an examination of how members of the value chain (including IP providers, EDA vendors, fabless chip makers, foundries, OSATs, OEMs, ... » read more

LLE-Aware Design Methodology To Avoid Timing And Power Pessimism

By Synopsys - 12 Mar, 2025 - Comments: 0

As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches. This paper describes a LLE-aware design methodology that mitigates the conservatism of co... » read more

Extracting Parasitic Impedance Of Semiconductor Power Modules

By Ansys - 12 Mar, 2025 - Comments: 0

As a key component in energy conversion system, power semiconductor devices are widely used in various applications, e.g., electric vehicles, renewable energy conversion, and uninterrupted power supplies. The trend for power converter design is always toward higher power density. Power modules that integrate multiple semiconductor devices can meet this demand. It also reduces the compl... » read more

← Older posts Newer posts →

category: Low Power-High Performance

category: IoT, Security & Automotive