Achieving Successful Timing, Power, And Physical Signoff For Multi-Die Designs


Multi-die designs using 2.5D and 3D technologies are increasingly important for a wide range of electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile. The multi-die architecture enables designers to mix dies from different foundries and technology nodes, including existing dies from previous projects. The resulting density and... » read more

How Engineering Simulation Drives Impact for Sustainability


For decades, engineering simulation has been the engineer’s Swiss Army knife for improving the speed and cost of developing new products as well as for bringing product performance to the next level. This report reveals that while simulation has already made a significant contribution to advancing sustainability, there is still so much potential to make an even greater impact. In the conte... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability


In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

AI Won’t Replace Subject Matter Experts


Experts at The Table: The emergence of LLMs and other forms of AI has sent ripples through a number of industries, raising fears that many jobs could be on the chopping block, to be replaced by automation. Whether that’s the case in semiconductors, where machine learning has become an integral part of the design process, remains to be seen. Semiconductor Engineering sat down with a panel of e... » read more

Why Your Data Center Needs a Digital Twin


The global digital twin market is on a rapid ascent, projected to skyrocket from $11.51 billion in 2023 to $137.67 billion by 2030. Spanning industries from aerospace to healthcare, digital twins are becoming an essential tool for efficient management. But what is a digital twin? Essentially, it’s a digital replica of any real-world entity—a product, system, or process—used for simulation... » read more

Research Bits: Jan. 13


High-temp electrochemical memory Researchers from the University of Michigan and Sandia National Laboratory propose a nonvolatile electrochemical memory that can store and rewrite information at temperatures over 1100°F (600°C), enabling it to continue working in environments as extreme as the surface of Venus. Instead of transporting electrons, the memory moves oxygen ions between layere... » read more

Research Bits: Jan. 7


Deep UV microLED for maskless lithography Researchers from the Hong Kong University of Science and Technology, Southern University of Science and Technology, and the Suzhou Institute of Nanotechnology developed an aluminum gallium nitride deep-ultraviolet microLED display array for maskless lithography.  They also built a maskless lithography prototype platform. "The team achieved key brea... » read more

Research Bits: Dec. 24


Growing multilayered chips Researchers from MIT, Samsung Advanced Institute of Technology, Sungkyunkwan University, and University of Texas at Dallas developed a method to fabricate a multilayered chip with alternating layers of semiconducting material grown directly on top of each other. The approach enables high-performance transistors and memory and logic elements on any random crystalline ... » read more

Research Bits: Dec. 16


Soft liquid metal vias Researchers from Virginia Tech and University of Pennsylvania found a way to create soft, flexible electric connections through circuit layers. The method could be used for soft robotics and wearable devices. The technique uses liquid metal microdroplets to create a stair-like structure that forms soft vias and planar interconnects through and across circuit layers wi... » read more

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips


By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

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