category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

European Mask And Lithography Conference 2024 Worth Attending
By Asmus Hetzel - 23 Jul, 2024 - Comments: 0

The European Mask and Lithography Conference (EMLC) 2024 recently was held in Grenoble, France, and had about 190 participants from a wide range of companies and institutions. Being relatively new to the field of lithography (my background is EDA, machine learning, optimization) and not being a fan of gigantic conferences, I thought it would be a good idea to visit this conference. My main p... » read more

CD Spec For Curvilinear Masks
By D2S - 23 Jul, 2024 - Comments: 0

Within the photomask industry, there's a major transformation from conventional Manhattan masks to more advanced curvilinear masks. Researchers from D2S and Micron Technology propose an equivalent CD spec for the curvy masks and use this spec to show that curvy masks have smaller mask variations than Manhattan masks. Find the technical paper here. Published June 2024. Linyong (Leo) Pang, ... » read more

New Interconnect Metals Need New Dielectrics
By Katherine Derbyshire - 23 Jul, 2024 - Comments: 0

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

Building A Sustainable And Diverse Semiconductor Workforce: Insights From ASMC 2024 Panel Discussion
By Krish Raghunath - 23 Jul, 2024 - Comments: 0

As the semiconductor industry works to attract talent to overcome its labor shortage, governments, educators, and the private sector must collaborate to make industry career opportunities more accessible for prospective employees. This concept provided the framework for a panel discussion during SEMI’s 35th annual Advanced Semiconductor Manufacturing Conference (ASMC) that took place in Alba... » read more

Intel Vs. Samsung Vs. TSMC
By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

Controlling Warpage In Advanced Packages
By Laura Peters - 24 Jun, 2024 - Comments: 1

Warpage is becoming a serious concern in advanced packaging, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field. Warpage plays a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with impro... » read more

Development Of Capacitance Measurement Unit For A System Level Tester
By BeomSeok Kim - 20 Jun, 2024 - Comments: 0

By BeomSeok Kim, SeongHwan Kim, Unki Kim, SeongBeom Cho, DongHo Seo, and SangHun Yun In back-end semiconductor processing it is important to improve the performance of semiconductors due to the limitations of miniaturization in front-end processes. To achieve this goal, the industry continues to invest in back-end processing and competition is fierce in advanced technology of back-end proces... » read more

Single Vs. Multi-Patterning Advancements For EUV
By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Virtual Exploration Of Novel Vertical DRAM Architectures
By Taeyon (TY) Oh - 20 Jun, 2024 - Comments: 0

In this article, we demonstrate a pathfinding technique for a novel Vertical DRAM technology. First, we identify important process parameters (defined by current semiconductor production equipment capabilities) that strongly impact yield. By using a virtual model, we then perform experimental optimization of the Vertical DRAM device across specific target ranges, to help predict and improve the... » read more

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