category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

Manufacturing Bits: Nov. 6
By Mark LaPedus - 06 Nov, 2018 - Comments: 0

FISH metrology The University of Illinois at Urbana-Champaign and the Mayo Clinic have developed a new molecular probe for use in imaging cells in living organisms. The probe combines conventional fluorescence in situ hybridization (FISH) metrology techniques with compact quantum dots. This technology can measure and count ribonucleic acid (RNA) in cells and tissue without organic dyes. ... » read more

Panel Fan-out Ramps, Challenges Remain
By Mark LaPedus - 05 Nov, 2018 - Comments: 0

After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors. However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are d... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 02 Nov, 2018 - Comments: 0

Chipmakers A U.S. federal grand jury has indicted Chinese DRAM maker Jinhua Integrated Circuit Co. (JHICC), Taiwan's UMC and three individuals, charging them with alleged crimes related to a conspiracy to steal, convey, and possess stolen trade secrets from Micron Technology for the benefit of a company controlled by the China government. In addition, the U.S. filed a civil lawsuit seeking... » read more

Manufacturing Bits: Oct. 30
By Mark LaPedus - 30 Oct, 2018 - Comments: 0

World’s smallest gyroscope The California Institute of Technology has developed the world's smallest optical gyroscope. The gyroscope is 500 times smaller than current devices, but it can detect phase shifts that are 30 times smaller than today’s systems. [caption id="attachment_24139584" align="alignleft" width="300"] The new optical gyroscope—shown here with grains of rice—is 5... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 26 Oct, 2018 - Comments: 0

Chipmakers GlobalFoundries and the Chengdu municipality have signed an amendment and changed the strategy of their joint fab investment in Chengdu, China. Originally, GlobalFoundries was supposed to install 180nm/130nm processes in the China-based 300mm fab. The partners have decided to bypass that technology. Intead, the fab will start with GlobalFoundries’ 22nm FD-SOI process. “Ch... » read more

CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

In-Cell Overlay Metrology By Using Optical Metrology Tool
By KLA - 26 Oct, 2018 - Comments: 0

By Honggoo Lee, Sangjun Han, Minhyung Hong, Seungyong Kima, Jieun Lee, DongYoung Leea, Eungryong Oh, and Ahlin Choi of SK Hynix, and Hyowon Park, Waley Liang, DongSub Choi, Nakyoon Kim, Jeongpyo Lee, Stilian Pandev, Sanghuck Jeon, John C. Robinson of KLA-Tencor Abstract Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced s... » read more

3D NAND: Challenges Beyond 96-Layer Memory Arrays
By Steve Shih-Wei Wang - 24 Oct, 2018 - Comments: 0

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working ... » read more

Manufacturing Bits: Oct. 23
By Mark LaPedus - 23 Oct, 2018 - Comments: 0

3D stacked finFETs At the upcoming 2018 IEEE International Electron Devices Meeting (IEDM), Imec is expected to present a paper on a 3D stacked finFET architecture. IEDM is slated from Dec. 1-5 in San Francisco. Imec’s technology is based what on the R&D organization calls sequential integration. Another R&D organization, Leti, calls it 3D monolithic integration. Regardless, the idea... » read more

A Crisis In DoD’s Trusted Foundry Program?
By Mark LaPedus - 22 Oct, 2018 - Comments: 0

The U.S. Department of Defense’s Trusted Foundry program is in flux due to GlobalFoundries’ recent decision to put 7nm on hold, raising national security concerns across the U.S. defense community. U.S. DoD and military/aerospace chip customers currently have access to U.S.-based “secure” foundry capacity down to 14nm, but that's where it ends. No other foundries provide similar “s... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy