category: Manufacturing, Packaging and Materials

category: Auto, Security & Edge AI

Impact Of U.S.-China Trade War
By Mark LaPedus - 23 May, 2019 - Comments: 0

The trade war between the United States and China is escalating and it is here to stay. Last year, the Trump administration started the trade war with China for basically two reasons. First, China has a massive trade surplus with the U.S. Second, U.S. companies have been the subject of IP theft in China, which has largely gone unchecked, according to the Trump administration. Many disagre... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing
By Pradeep Nanja - 23 May, 2019 - Comments: 0

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

Multifunctional Materials Enable Single-Layer Temporary Bonding And Debonding
By Luke Prenger - 23 May, 2019 - Comments: 0

Many new wafer-level packaging (WLP) technologies involve the processing of thin wafers that must be mechanically supported during the manufacturing flow. These technologies include fan-out wafer-level packaging (FOWLP), fan-in wafer-level chip-scale packaging (FI-WLCSP), 3-D FOWLP, 2.5-D integration with interposer technology, and true 3-D IC integration using through-silicon via (TSV) interco... » read more

Improved Accuracy And Robustness For Advanced DRAM With Tunable Multi-Wavelength Imaging Scatterometry Overlay Metrology
By KLA - 23 May, 2019 - Comments: 0

By Honggoo Lee, Sangjun Han, Minhyung Hong, Jieun Lee, Dongyoung Lee, Ahlin Choi and Chanha Park of SK Hynix, and Dohwa Lee, Seongjae Lee, Jungtae Lee, Jeongpyo Lee, DongSub Choi, Sanghuck Jeon, Zephyr Liu, Hao Mei, Tal Marciano, Eitan Hajaj, Lilach Saltoun, Dana Klein, Eran Amit, Anna Golotsvan, Wayne Zhou, Eitan Herzl, Roie Volkovich and John C. Robinson of KLA. Abstract Overlay process c... » read more

Q1 2019 Unit Drop Impacts Wafer Demand For 2019
By Joanne Itow - 23 May, 2019 - Comments: 0

The Semico Wafer Demand Model update for Q1 2019 now results in a 5.9% decline in wafer demand for 2019. Along with process technology and productivity, Semico’s Wafer Demand Model is highly dependent on semiconductor unit sales. In the Q1 2019, total semiconductor units dropped by 7.4% compared to Q4 2018 and 3.8% compared to Q1 2018. The drop in units is significant because of the broad spe... » read more

Small Critical Subsystems Suppliers Outperform In Downturns
By Julian West - 23 May, 2019 - Comments: 0

Clouds continue to persist over the semiconductor supply chain with little sign of lifting. In March, the decline in week-over-year chip sales appeared to be slowing, providing a glimmer of hope for the beginning of a new cycle. However, the recent rapid escalation of the tariff war between the U.S. and China heaped more uncertainty on the industry and visibility continues to remain low. Rev... » read more

SiC Demand Growing Faster Than Supply
By Mark LaPedus - 23 May, 2019 - Comments: 2

The silicon carbide (SiC) industry is in the midst of a major expansion campaign, but suppliers are struggling to meet potential demand for SiC power devices and wafers in the market. In just one example of the expansion efforts, Cree plans to invest up to $1 billion to increase its SiC fab and wafer capacities. As part of the plan, Cree is developing the world’s first 200mm (8-inch) SiC f... » read more

Partitioning In 3D
By Katherine Derbyshire - 23 May, 2019 - Comments: 2

The best way to improve transistor density isn't necessarily to cram more of them onto a single die. Moore’s Law in its original form stated that device density doubles about every two years while cost remains constant. It relied on the observation that the cost of a processed silicon wafer remained constant regardless of the number of devices printed on it, which in turn depended on litho... » read more

New Imaging Tech Finds Buried Defects
By Shinsuke Mizuno - 23 May, 2019 - Comments: 0

By Shinsuke Mizuno and Vadim Kuchik Defects and contamination on the wafer can slow process development times and limit performance and yield. As chips get more complex, more defects can become buried within the increasing number of layers in the design. Finding and analyzing these buried defects is a major challenge for the industry, especially during the early learning cycles of new manufa... » read more

3D NAND Race Faces Huge Tech And Cost Challenges
By Mark LaPedus - 23 May, 2019 - Comments: 8

Amid the ongoing memory downturn, 3D NAND suppliers continue to race each other to the next technology generations with several challenges and a possible shakeout ahead. Micron, Samsung, SK Hynix and the Toshiba-Western Digital duo are developing 3D NAND products at the next nodes on the roadmap, but the status of two others, Intel and China’s Yangtze Memory Technologies Co. (YMTC), is les... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy