Managing Thermal-Induced Stress In Chips


At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Devices And Transistors For The Next 75 Years


The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

2D Semiconductor Materials Creep Toward Manufacturing


As transistors scale down, they need thinner channels to achieve adequate channel control. In silicon, though, surface roughness scattering degrades mobility, limiting the ultimate channel thickness to about 3nm. Two-dimensional transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are attractive in part because they avoid this limitation. With no out-of-plane dangling bonds and at... » read more

Tomorrow’s Semiconductor Workforce


With tens of billions directly allocated to spur growth in this essential industry, now is the time for us to focus on a critical challenge: ensuring that as this industry grows exponentially, we create a pipeline for the next generation of semiconductor workers, from the manufacturing floor to the design suites. The semiconductor industry’s growth will ripple throughout the nation, creating ... » read more

Modeling Analytics for Computational Storage


This paper discusses the expected performance benefits of offloading some important basic database operations — namely Scan, Filter and Project — to computational storage. We evaluate the performance estimate model using TPC-DS workload and two database engines running on Hadoop clusters: SPARK- SQL and Presto. This paper is organized as follows: after covering previous computational sto... » read more

American Innovation, American Growth: A Vision For The National Semiconductor Technology Center


In the paper, MITRE Engenuity and The Semiconductor Alliance take on the task of defining the principles by which the NSTC should be established to ensure that the U.S. makes the most of this opportunity to bring substantial funding and cross-sector collaboration to bear on the challenge of driving U.S. leadership in semiconductors for decades to come. Click here to read more. » read more

Week In Review: Semiconductor Manufacturing, Test


Chips for consumer devices are down, but the overall chip industry is actively preparing for the next phase of growth. Worldwide silicon wafer shipments, which are an aggregate view of all the various semiconductor segments, hit an all-time high in 2022, increasing 4% to 14,713 million square inches (MSI). Wafer revenue, meanwhile, rose 9.5% to $13.8 billion over the same period, SEMI reported ... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics


Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Week In Review: Semiconductor Manufacturing, Test


Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

Week In Review: Semiconductor Manufacturing, Test


Starting in 2025, SEMICON West will move to Phoenix for a five-year annual rotation. And in 2024, it will shift dates from July to October. This year’s conference will still take place July 11 to 13 at the Moscone Center. Phoenix will first host SEMICON West on October 7-9, 2025. Thereafter, it will be held at the Moscone Center in San Francisco on the alternating years and over the long term... » read more

← Older posts Newer posts →