Big Changes Ahead For Chip Technology And Industry Dynamics

How customization, complexity, and geopolitical tensions are upending the global status quo.


Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle solutions at Siemens EDA. What follows are excerpts of that conversation, which was held in front of a live audience at the recent SEMI Industry Strategy Symposium. To view part one of this discussion, click here.

SE: What impact is custom silicon, particularly among the large systems companies, having on industry dynamics?

Fried: Ten years ago, if you developed an etch process, you had your spec. There were a couple targets, you characterized the errors, but that was it. Now, because of this customization and the flexibility you need to provide, we’re creating processes and deeply understanding sensitivities and how to control and modify those processes in manufacturing. We’re providing models and virtualization around those processes to allow our customers to customize on the fly. And then, we can keep adding layers of control mechanisms on the equipment to enable that adaptation and flexibility. So if you look at the different roadmaps and product optimizations, it’s enabled us to do a lot more at every level of that chain. And I’m just talking next processes with their models and controls and sensitivities. But every step along that chain requires that same type of additional understanding and flexibility.

SE: What happens when you move into advanced packaging in three dimensions?

Van den Hove: It demands more cooperation and more interaction, because you have more players involved. In order to be able to continue with these different roadmaps, we will have to bring different communities together to work on the interfaces for chiplets. New tools will be required to enable the integration of different versions of chiplets. And over the next couple of years we will need high-precision bumping with hybrid bonding. This provides new opportunities for tools development. You may have one company that has a lot of expertise in very precise alignment, and another company with expertise in bumping. This creates opportunities for bringing together the entire ecosystem.

Gupta: If you look at 3D-ICs, the market is moving toward the UCIe standard for chiplets. You see tools from all the EDA companies. But what got us here was a lot of early access program kind of work. We worked closely with big companies at the forefront of advanced packaging. The trend we see is that with innovation at the packaging level, and at the boundary level, there is a need for EDA follow that innovation very closely, and then to find general-purpose solutions. You have these early innovators that you work with, and then you make something that’s more readily usable.

SE: Most of the 3D packaging has involved chiplets developed by a single vendor. What happens when we get into a commercial chiplet market?

Fried: When I was at IBM, we had these massive monolithic server chips — multi-core, lots of logic, lots of memories, embedded DRAM. So we started thinking about whether this really lends itself to some type of segregation and 3D optimization with the best memory, the best logic. That would allow us to start solving some of the footprint problems, as well. Twenty years ago, one of the biggest problems was that we didn’t have the EDA tools to do the analysis to see where the optimization point would be. We think there’s some benefit to this, but how do we even explore the options and segment this thing? How do you spec out the memory, the analog, or the I/O, and then re-integrate it all into 3D and determine whether there is enough value to that optimization to go through the pain of the process challenges. It has taken a really, really long time to get to the point where the system integrators, the chip integrators, can get through that analysis and have the EDA tools. You need standards to get to the point where you have the options to go explore. Those standards have to be based around technologies that are possible to integrate. You can’t create a standard around some fantasy integration. That’s worthless, and it has happened in our industry before. You have to put all these things together with yieldable, manufacturable, functional technologies with a standard and with a tool. You try to give options and enable those optimization points for the system integrators. But that requires getting multiple different companies, vendors, and disciplines all talking and collaborating, and it’s one of the biggest challenges right now. It’s not just bilateral or trilateral cooperation. It’s seven different parts of the supply chain, and they all have to move together. That’s extremely difficult. That’s why we’re at imec. We’re trying to sort some of these issues in a pre-competitive environment. But getting 10 companies to sing the same tune is a challenge.

van den Brink: Cooperation is good, but don’t overdo it. Simplification of cooperation has value. This is how you compartmentalize a system so that EDA can optimize it. This is how you do 3D integration. The chip guys and the foundry guys have to determine how they compete, which foundries they use. And where they don’t know how to do something, they should be allowed to go through suppliers. If you look at the commoditization of memory, which has been taking place for the last 50 years, the interface determines a large part of the performance for high-performance computing. But it could never get beyond the commodity box because the interface wasn’t there, and the system integrators didn’t allow that interface to be transparent. It’s only recently where the industry came together to define the interface. So where this level of cooperation is necessary, these goals must be supported by standardization. That way everybody has a common language with which they can participate in this optimization.

SE: There is more demand for compute power, and there are more ways to achieve it, from advanced packaging to moving compute closer to memory. So everything is changing, including how many steps there are for each process in the foundry. Do you see that trend continuing?

van den Brink: If you if you look back, with Dennard scaling everything was simple. You could you get everything. Now you’re forced to get smarter, because if you don’t you will not have value in your product. Hence, you now have to really determine the hierarchy in this supply chain. Where do I differentiate and where do I go? And can the supply chain deal with this? Without total system integration optimization — and this will continue for at least the next 10 years — you will see adjustments because of the need to get the system performance and the value for the money.

Fried: The technology requirements of NAND and DRAM have not shifted away from commodity memory technology. And yet people are using commodity memory structures to demonstrate in-memory computing in order to justify this specialization/optimization of memory. I don’t think we’ve seen people producing memory that is specialized and specifically designed for memory compute quite yet. That’s probably the next phase, where some of these architectures and some of these systems start to truly benefit from that. And it drives different technology specifications, whether that is higher density or higher performance, or how many levels per bit. Is it a two-, three-, or four-layer bit? And does that actually help? Does playing that game actually help in-memory compute? We don’t know yet. We’re using a lot of these structures to try to understand and justify that, but they’re not at all optimized for that.

Van den Hove: It’s clear that it’s time to go in that direction, both for in-memory compute and for memory-on-logic. That’s why we need to look at complete system technology integration. For the workloads that you need to process, you don’t know what technology solutions you have to come up with or what standards are required. That’s why we’re investing a lot in R&D. Solutions will be different for different applications.

SE: How do we make sure these systems will be reliable?

Gupta: By observing at different points. What we’ve been doing is measuring the quality of the chips by looking at performance metrics. But going forward, we have to look at the software efficiency and the workload efficiency for which this chip was intended. For example, data center reliability today is measured by the longevity of the chip. But is it doing bad math? When you design a chip, you say this is a known-good-die in a known-good-package. But then, because of some workloads, that chip could be doing bad math. The way EDA is looking at it is you need to observe this problem in its natural environment, under stressful conditions, in a certain temperature, voltage, process environment. That requires monitoring, and this is the lifecycle portion of of EDA. We are not just stopping at GDSII. We are looking beyond that and collaborating with production and other systems.

Fried: The EDA part of our business is further ahead than a lot of the process integration in factories. The EDA industry has figured out how to provide simulation, automation, and virtualization to solve a lot of those problems to make the foundries and the designers and the system folks collaborative. We have to learn that lesson and drive simulation, virtualization, and automation all the way down through the value stack to enable collaboration and connect the different contributors — litho and etch through virtualization; full-fab integration with virtualization, so you can take that whole fab integration and all the variations. And if we have digital twins that we can simulate, from there we can connect that to the EDA systems. We’re not going to do this by trial and error. We’re not going to just fabricate stuff until it works. We have to learn some lessons from EDA and extend that to the rest of the industry if we’re going to be continue being successful.

SE: With all the massive government investments and the move to stabilize the supply chain with on-shoring and re-shoring, it appears that governments want a say in what’s going on. How will this affect chip manufacturing?

van den Brink: Globalization was a comfortable and dominant attribute at the center, but we’re starting to see some compartmentalization on the sides. As a result, the learning and the cooperation will be challenged, and the effectiveness of us moving forward and breaking down walls will be more difficult. I don’t deny the need to make sure manufacturing is spread equally, but it should not impact global cooperation. When I started in this business, a stepper was made by 10 people in a research lab. Today we have 50,000 engineers at ASML working at the sub-system level and system level, and they all have to talk. The goals for everyone need to be established where everyone feels comfortable with them.

Van den Hove: We should use these initiatives where the governments have come in as opportunities to tackle some of the real issues that we talked about — promoting collaboration among the various layers in the value chain, but also laterally across the various players. These resources are limited, and they should not be used to duplicate and decouple what has been built up over decades. We should use it to promote cooperation among like-minded countries.

Fried: If we just take that money, hand it out and scale up, we will have wasted a huge opportunity. Obviously, people will get their piece of that funding to scale up, and some of them will be quite happy with that. But if we don’t use this to fund collaboration, to be more inclusive, to deepen the connections with research institutions in our country and maybe across the Atlantic — if we don’t begin to ‘crowd-source’ innovation more efficiently — then we will have wasted a huge opportunity. EDA and the foundry fabless model allowed a whole new community of people to design chips that never had access to that before. So it was a business model and then a set of tools that crowd-sourced innovation. If you go talk to the university professors, most of them will tell you it’s very hard to find research topics right now because the big companies are doing it all and they can’t really contribute that much anymore. That’s a horrible loss. If we include the research institutions, giving them tools and capabilities and access, we can do something very, very different than what’s been done in the last 30 years. Instead of just scaling up, we can drive a more differentiated industry from this opportunity. And it’s not just from an innovation perspective. My personal opinion is the best way to develop a workforce is by opening up that opportunity to a much larger group of people.

van den Brink: It’s not just about money. The issue is the complexity of system scaling. You can only be successful by not wasting any talent in this whole value proposition. People need to realize the success of the semiconductor industry has been due to the ability of people to work together, and that will be necessary to get to the next phases. The need to have open communication, open collaboration, will be even more true in the future.

Van den Hove: The challenges have become so big that we need to try to use all these resources, and attract as many resources as possible, to build critical mass together.

Gupta: For EDA, government involvement is really two things. One is a barrier, which is the short-term issue. Who can I sell to and what can I sell? But there is also an opportunity. One is just more companies around the world, like we’re starting to see in China. It’s localization, but ultimately it will make the industry stronger. There also is another element, which is RISC-V, and the ISA that’s also being commoditized. The ability of students to build chips without having to pay a fee is a trend we’re watching very closely. RISC-V will enable more people to come into electrical engineering.

Collaboration Widens Among Big Chip Companies
Top equipment and tools vendors see need for earlier cooperation as complexity rises for advanced nodes and packages (part 1 of the above discussion).

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