SiPs: The Best Things in Small Packages

By Laura Peters - 20 Oct, 2022 - Comments: 0

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures

By Adele Hars - 20 Oct, 2022 - Comments: 0

Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter... » read more

What’s Different About Next-Gen Transistors

By Katherine Derbyshire - 20 Oct, 2022 - Comments: 0

After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

Additive Techniques For Flexible Hybrid Electronics Packaging And Integration With Human Body

By Gity Samadi - 20 Oct, 2022 - Comments: 0

By Gity Samadi and Paul Semenza Flexible hybrid electronics (FHE) has spawned the development of novel packaging techniques to overcome the application limitations of the rigid boards, high-temperature solders, bulky component packages, and insertion processes used in traditional printed circuit boards. Thin, flexible substrates, bare die, and combinations of printed and small-format package... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Production Testing Of Discrete Power Products

By Vineet Pancholi - 20 Oct, 2022 - Comments: 0

By Vineet Pancholi and Dennis Dinawanao Metal Oxide Silicon Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Bipolar Junction Transistors (BJTs), diodes, and application specific multi-transistor packaged modules are some of the more popular discrete products. Switches control the flow of current within a circuit. MOSFETs are a building block of most electronic... » read more

Realization Of Sub-30-Pitch EUV Lithography Through The Application Of Functional Spin-On Glass

By Brewer Science - 19 Oct, 2022 - Comments: 0

Photoresist metrics such as resolution, roughness, CD uniformity, and overall process window are often aimed to realize the full potential of EUV lithography. From the view of the materials supplier, improvements over the aforementioned metrics can be achieved by optimizing the functional materials used under the resist. The underlayers can significantly enhance the resist performance by provid... » read more

Metal Oxide Resist (MOR) EUV Lithography Processes For DRAM Application

By TEL - 19 Oct, 2022 - Comments: 0

This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination... » read more

2022 Survey: Luminaries Report Positive EUV Impact On Mask Trends

By eBeam Initiative - 19 Oct, 2022 - Comments: 0

The eBeam Initiatives 11th Annual Luminaries Survey from July 2022 shows • EUV viewed as a positive impact for mask revenue • EUV remains the top reason for purchasing multi-beam mask writers • Confidence remains high in ability to make curvilinear masks with availability of multi-beam mask writers less of an issue this year Click here to read the survey results. » read more

Pathfinding By Process Window Modeling

By Coventor - 19 Oct, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D®. The ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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