category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

Why Changes In Computing Are Driving Changes In Photomasks
By Ed Sperling - 18 Oct, 2022 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 14 Oct, 2022 - Comments: 0

The United States imposed further export controls aimed at preventing foreign firms from selling advanced chips to China or supplying Chinese firms with semiconductor processing tools. Under new regulations, companies looking to supply Chinese chipmakers with advanced manufacturing equipment (<14nm) must first obtain a license from the U.S. Department of Commerce. Officials noted that they h... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 07 Oct, 2022 - Comments: 0

Micron selected Syracuse, New York as the site for its new megafab complex, which is expected to create 9,000 company jobs and 40,000 construction and supply chain jobs. President Biden called it “another win for America.” The chip manufacturing facility will be the nation’s largest, including a 7.2 million square foot complex and 2.4 million square foot of cleanroom. Site preparation wil... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 23 Sep, 2022 - Comments: 0

On Sunday, a 6.8-magnitude earthquake struck the southeast region of Taiwan, causing devastation. TSMC officials reported “no known significant impact for now.” Market research firm TrendForce arrived at a similar conclusion based on its analysis of individual fabs. The Biden administration announced appointment of the leadership team charged with implementing the US CHIPS and Science Ac... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 16 Sep, 2022 - Comments: 0

President Biden signed an executive order on Sept. 15, limiting foreign investments in U.S. technology by "competitor or adversarial nations" that are deemed a threat to national security. In the past, the Committee on Foreign Investment in the United States (CFIUS) largely limited its actions to the sale of U.S. companies. The new directive expands that to include investments involving "U.S. s... » read more

Improving Redistribution Layers for Fan-out Packages And SiPs
By Laura Peters - 15 Sep, 2022 - Comments: 2

Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO
By Nathan Whitchurch - 15 Sep, 2022 - Comments: 0

Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication
By Coventor - 15 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

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