Metrology Advances Step Up To Sub-2nm Device Node Needs


Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

From Reaction To Prevention In Data Center RAS


The rise of artificial intelligence (AI), cloud services, and IoT has fueled the rapid expansion of hyperscale data centers. These massive facilities house thousands of servers, all working to support an increasingly digital world. But as the scale of data centers grows, so too does the need for reliable and high-performance semiconductors. Semiconductor failures and inconsistencies can cause s... » read more

Complex Heterogeneous Integration Drives Innovation In Semiconductor Test


Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The automated test equipment (ATE) industry is responding, developing and utilizing more sophisticated test equipment capable of handling the diverse functionalities and interfaces needed to test heterogeneous... » read more

New Challenges In IC Reliability


Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips, how it is changing, and where the new challenges are, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech soluti... » read more

Redefining RAS in Datacenters with Real-Time Health Monitoring


Abstract Hyperscale datacenters require intense computational power for compute-intensive tasks, such as AI, data analytics, machine learning, and big data processing. They leverage parallel processing across multiple computers, in high-density servers, to handle complex tasks efficiently. This uses specialized, powerful processors and training and inference of specific GPUs or ASICs. Such c... » read more

ML Model Usage For Various Life Stages Of Semiconductor Test


By Shinji Hioki and Ken Butler From development through high volume manufacturing (HVM), semiconductor manufacturers’ pain points change based on the life stages. Each stage requires different types of applications to help with business needs. At the early stage, where the design and process are still immature, understanding the root causes of maverick material and implementing fixes is th... » read more

Signals In The Noise: Tackling High-Frequency IC Test


The need for high-frequency semiconductor devices is surging, fueled by growing demand for advanced telecommunications, faster sensors, and increasingly autonomous vehicles. The advent of millimeter-wave communication in 5G and 6G is pushing manufacturers to develop chips capable of handling frequencies that were once considered out of reach. However, while these technologies promise faster ... » read more

Achieving Zero Defect Manufacturing Part 3: Prevention Of Defects


The concept of zero defect manufacturing has been around for decades, arising first in the aerospace and defense industry. Since then, this manufacturing approach has been adopted by the automotive industry, and it has only grown in importance as the sector transitions to electric vehicles. Given the role semiconductors play in today’s vehicles, and will play in the future, it is no surprise ... » read more

Taking Data Center Serviceability To The Next Level


It is no secret that Artificial Intelligence (AI) workloads are driving an exponential growth in the scale of supercomputers and data centers. Training the latest LLM (Large Language Model), for instance, typically requires thousands of specialized processing cores running at full speed. As these models get more advanced with each generation, they need additional compute performance to absorb a... » read more

Defect Challenges Grow At The Wafer Edge


Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

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