category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Encapsulating Wearable Sensors Using A Pre-Mixed Two-Part Epoxy
By Anthony Buzzerio - 10 Mar, 2026 - Comments: 0

By Anthony Buzzerio, Venkat Nandivada, and Rohit Ramnath The growing field of wearable medical technology relies heavily on miniaturized sensors capable of providing accurate and continuous physiological data. Ensuring the long-term reliability and performance of these sensors — often subjected to demanding conditions including physical stress, thermal fluctuations, and exposure to bodily ... » read more

Automated Measurement Recipes for Photothermal AFM‑IR
By Bruker - 10 Mar, 2026 - Comments: 0

Recipe‑based automation for atomic force microscopy (AFM) workflows ensures consistent, repeatable data acquisition, reduces operator dependency, and streamlines complex measurement routines. Bruker’s AutoMET automation software, widely adopted for conventional AFM characterization, now also brings automation to nanoscale IR (nanoIR) spectroscopy and imaging. AutoMET provides except... » read more

Addressing Semiconductor Cybersecurity Challenges through Robust Industry Standards and Globally Secure Frameworks
By PDF Solutions - 10 Mar, 2026 - Comments: 0

This presentation addresses critical cybersecurity challenges in semiconductor manufacturing by outlining current industry standards (SEMI E187, E188, E191) and their implementation through SMCC workgroups. It identifies key gaps in existing frameworks—particularly the inadequacy of current equipment connectivity standards for distributed collaboration and the scalability challenge of custom ... » read more

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

Catching Critical Defects In TSVs And Stacked Chips
By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Beyond Optical: A New E-Beam Inspection For Advanced Chips
By Christophe Begue - 10 Feb, 2026 - Comments: 0

The semiconductor industry is defined by its relentless pursuit of smaller, faster, and more powerful chips. As we push into advanced 3D architectures like gate-all-around (GAA) transistors, a critical challenge emerges: finding the defects that kill yield. Many of these flaws are deeply buried within complex structures and impossible to see with traditional optical inspection. This creates ... » read more

Resistance In Advanced Packages Is Now A System-Level Problem
By Gregory Haley - 10 Feb, 2026 - Comments: 0

Key Takeaways Kelvin measurement, which has been in use for decades, is no longer sufficient for addressing resistance in complex chips. The problem is that resistance is no longer concentrated in transistors, and where it does show up isn't always consistent or obvious. Traditional pass/fail approaches need to be replaced by more granular and flexible analytics and methodologies. ... » read more

Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance
By PDF Solutions - 10 Feb, 2026 - Comments: 0

Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. The presented study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7nm FinFET transistors. Variations in critical dimension ... » read more

Are You Using Structural Patterns In An SLT Environment?
By Peter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

The Surface Metrology Decision Guide
By Bruker - 10 Feb, 2026 - Comments: 0

The Surface Metrology Decision Guide empowers readers to choose techniques and confidently engage with equipment providers. What’s inside: A side-by-side comparison of the resolution, strengths, and limitations of common surface metrology techniques An in-depth look at advances in and practical considerations for white-light interferometry (WLI) Summary chart of WLI objectives, ma... » read more

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