The Role Of EDA In AI

By Brian Bailey - 17 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

From AI Algorithm To Implementation

By Brian Bailey - 10 Apr, 2019 - Comments: 0

The Automation Of AI

By Brian Bailey - 28 Mar, 2019 - Comments: 0

Data-Driven Verification Begins

By Ed Sperling - 27 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss data-driven verification with Yoshi Watanabe, senior software architect at Cadence; Hanan Moller, systems architect at UltraSoC; Mark Conklin, principal verification engineer at Arm; and Hao Chen, senior design engineer at Intel. What follows are excerpts of that conversation, which was conducted in front of a live audience at DVCon. (L-R) Yosh... » read more

EUV Mask Readiness Challenges

By Mark LaPedus - 21 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and photomask technologies with Emily Gallagher, principal member of the technical staff at Imec; Harry Levinson, principal at HJL Lithography; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials; and Aki Fujimura, chief ... » read more

Partitioning Drives Architectural Considerations

By Ann Mutschler - 25 Feb, 2019 - Comments: 0

Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

Building Security Into RISC-V Systems

By Ed Sperling - 30 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. Part one is here. (This is the second of two parts.) L-R: Joseph Kiniry, Helena Handschuh, Richard Newell. SE: Some of the new applications for hardware designs are tied to AI, d... » read more

Planning For 5G And The Edge

By Ed Sperling - 23 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss 5G and edge computing with Rahul Goyal, vice president in the technology and manufacturing group at Intel; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; Rob Aitken, R&D fellow at Arm; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows are excerpts of that conversation. Part one i... » read more

Process Variation And Aging

By Ann Mutschler - 17 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; and Naseer Khan, vice president of sales at M... » read more

Machine Learning For IC Production

By Mark LaPedus - 16 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss artificial intelligence (AI), machine learning, and chip and photomask manufacturing technologies with Aki Fujimura, chief executive of D2S; Jerry Chen, business and ecosystem development manager at Nvidia; Noriaki Nakayamada, senior technologist at NuFlare; and Mikael Wahlsten, director and product area manager at Mycronic. What follows are excerpt... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: Round Tables

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