Design Flow Challenged By 3D-IC Process, Thermal Variation


3D-ICs are proving a challenge even for designers accustomed to dealing with power and performance tradeoffs, but they are considered an inevitable migration path for leading-edge designs due to the compute demands of AI and the continual shrinking of digital logic. 3D-ICs are widely viewed as the way to continue scaling beyond the limits of planar SoCs, and a way to add more heterogeneous d... » read more

Investing in EV Battery Testing — Benefits for EV Battery Designers


Phasing out gas-powered internal combustion engines (ICE) and moving towards clean energy electric vehicles (EVs) brings substantial technology investments to deliver EVs to the mainstream market. Government legislation to eliminate or limit the production of ICEs by 2035 is creating a surge in demand for the EV ecosystem. This in turn, is driving demand for more efficient ways of EV battery sy... » read more

Blog Review: June 26


Cadence's Neelabh Singh examines the Gen4 link recovery mechanism in USB4 Version 2.0, an autonomous process that is initiated by a router when it encounters uncorrectable error events, and identified verification challenges. Synopsys' Gary Ruggles and Priyank Shukla highlight improvements to PCIe 7.0 that will enable secure data transfers and boost bandwidth for the next generation of AI an... » read more

U.S. Proposes Restrictions On Tech Investments In China


The U.S. proposed new regulations to curtail American investments in Chinese technologies that pose a national security threat, specifically calling out semiconductors and microelectronics, quantum information technologies, and AI. The draft regulations come nearly a year after the Biden administration issued an executive order prohibiting investments in sensitive technologies used to accele... » read more

Blog Review: June 19


Siemens' John McMillan and Todd Burkholder suggest using an automatic formal-based approach to verifying chiplet package connections early in the design process. Cadence's Veena Parthan explores the intricacies of wind tunnel testing in automotive design and how the collaborative relationship between computational fluid dynamics (CFD) and wind tunnels has resulted in accelerated and more nua... » read more

Promises And Pitfalls Of SoC Restructuring


As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, explains why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interface... » read more

Blog Review: June 12


Cadence's Deep Mehta finds that PCIe 6.0 switches need advanced verification strategies that delve deeper than basic functionality, such as generating backpressure traffic to identify potential performance bottlenecks and ensure the switch operates optimally in real-world scenarios. Siemens' Reetika explains why proper management and verification of reset domain crossing (RDC) paths are cruc... » read more

Blog Review: June 5


Cadence's Neelabh Singh provides an overview of the low power entry and exit flows in USB4 Version 2.0 link speed and how they have been simplified by making low power entry uni-directional and removing the need for certain handshakes for low power exit of the re-timers. In a podcast, Siemens' Steph Chavez chats with Daniel Beeker of NXP about the foundational importance of power distributio... » read more

Why IC Design Safety Nets Have Limits


Experts at the Table: Semiconductor Engineering sat down to discuss different responsibilities in design teams and future changes in tools with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager at Siemens EDA; Dirk Seynhaeve, vice president of business development at Sigasi; Simon Davidmann, formerly... » read more

Ensuring Your Power And Ground Nets Are Correctly Connected


In most chip designs, the power and ground nets are likely your largest and most important nets. If any devices are not properly connected, then you cannot expect them to function as expected. Amongst the many problems that can occur to power and ground involves the connections to the well areas of your design that power all the bulk connections to your devices. Well regions connectivity is oft... » read more

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