category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Jan. 7
By Jesse Allen - 07 Jan, 2026 - Comments: 0

Cadence's Reela Samuel presents an overview of through-silicon vias, including structure, pitch, and electrical behavior, key layout rules such as keep-out zones and stress constraints, and how TSV parasitics influence bandwidth, latency, and system-level performance. Siemens' Andras Vass-Varnai identifies five thermal trends to watch and how they’ll reshape design and packaging workflows ... » read more

Blog Review: Dec. 24
By Jesse Allen - 24 Dec, 2025 - Comments: 0

Cadence's Jakob Engblom shares highlights from the recent SDV Europe conference, including why software-defined vehicles will require much closer, faster collaboration between suppliers and customers, with virtualization for software development and testing taking on a key role, as well as API questions and tire sensors. Synopsys' Tom De Schutter and Marc Serughetti predict that new cars wil... » read more

Software-Defined Hardware-Assisted Verification: Scaling To Quadrillions Of Cycles For Verification In The AI Era
By Frank Schirrmeister - 23 Dec, 2025 - Comments: 0

The semiconductor industry is at an inflection point. The convergence of advanced multi-die architectures, AI-driven workloads, and rapidly evolving interface protocols is creating unprecedented design complexity. At the same time, market pressures demand faster time-to-market and higher performance, leaving little room for error. From data center to edge developments, users have to run softwar... » read more

PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2
By Cadence - 23 Dec, 2025 - Comments: 0

As PCI Express (PCIe) evolves through Gen4, Gen5, and now Gen6, the complexity of high-speed design continues to grow. Signal and power integrity, equalization, clocking, and compliance — every layer of the PCB must be optimized for speed and reliability. The PCIe Design Guide – Q&A (Part 2) expands on the first volume with a deep dive into simulation, validation, and compliance, a... » read more

3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications
By Reela Samuel - 23 Dec, 2025 - Comments: 0

The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver economically, vertical integration and heterogeneous system design are no longer experimental; they are becoming foundational. Advanced packagin... » read more

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Minimizing Design Risk: Rapid Feasibility Exploration For Multi-Die Designs
By Synopsys - 23 Dec, 2025 - Comments: 0

Multi-die design is revolutionizing semiconductor innovation, offering unprecedented flexibility, but also introducing complexity. What if designers could spot and solve critical issues, such as IR drop, electromigration, and thermal impact before they ever reach the design implementation stage? In this white paper, we explore how rapid, comprehensive feasibility exploration enables desi... » read more

The Power Of Shift-Left DRC Verification With Calibre nmDRC Recon
By Siemens EDA - 23 Dec, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Autonomous ASIC Root Cause Analysis
By Mehir Arora - 23 Dec, 2025 - Comments: 0

By Mehir Arora and Zackary Glazewski Over 50% of frontend ASIC hardware engineering time is spent on debugging and root cause analysis, spent churning through millions of lines of code and terabytes of waveform data. Despite this, there are no existing solutions for autonomous root cause analysis that use both code and waveform data. ChipAgents Root Cause Analysis (ChipAgents RCA) is the fir... » read more

Setting Vmin With Transistor-Level PDN Telemetry
By Hans Yeager - 23 Dec, 2025 - Comments: 0

By Hans Yeager and Aakash Jani Curious about how to precisely determine the optimal voltage-regulator setpoints for your System-on-Chip (SoC)? In this video, we dive into how transistor-level Power Delivery Network (PDN) telemetry can revolutionize your approach to power, performance, and reliability. The voltage you set at the regulator (V-Min-VR) is rarely what the transistors actually ... » read more

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