category: System-Level Design

category: Auto, Security & Edge AI

Extraction Challenges of CFET and Backside Power Delivery
By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

Blog Review: Mar. 25
By Jesse Allen - 25 Mar, 2026 - Comments: 0

Synopsys' Jayraj Nair checks out how a model-based systems engineering workflow can help manage the complex multiphysics analysis needed to optimize heterogeneous systems. Siemens' Melville Bryant explains the difference between semiconductor traceability and tracking and why they're both essential, especially for complex multi-die devices. Cadence's Jamdagni Trivedi checks out VIP option... » read more

Building an AI Chip: Security, Software Development, and Lifecycle Management
By Synopsys - 25 Mar, 2026 - Comments: 0

The third white paper in our series, "Building an AI Chip" delves into the critical aspects of ensuring robust security and efficient software development for AI chips. As AI applications become increasingly integrated into everyday systems, the need for secure and reliable chip designs is paramount. This paper outlines essential strategies for safeguarding AI chip development, optimizing softw... » read more

Blog Review: Mar. 18
By Jesse Allen - 18 Mar, 2026 - Comments: 0

Cadence's Jamdagni Trivedi explains the UALink Protocol Level Interface, which defines how devices exchange data and control information, and shares insights into its structure, functionality, and significance in multi-node accelerator systems. Synopsys' Dustin Todd argues that AI sovereignty will be defined by and built on strategic interdependence, where countries develop and retain meanin... » read more

How AI Will Automate Chip Design
By Ed Sperling - 17 Mar, 2026 - Comments: 0

AI has been used in EDA for many years for the core algorithms in tools, but it's getting smarter and more optimized with the rollout of generative and agentic AI. As it evolves and improves, hardware engineers are finding ways to leverage it for more complex tasks. Ziyad Hanna, corporate vice president at Cadence, talks about five levels of autonomy in chip design that mirror those in the auto... » read more

AI Design Reshapes Data Management
By Ann Mutschler - 16 Mar, 2026 - Comments: 0

Key takeaways: Integrating AI into chip workflows is pushing companies to overhaul their data management strategies, shifting from passive storage to active, structured, and machine-readable systems. As training and inference workloads grow, data movement, congestion, and energy efficiency become the dominant challenges, often surpassing raw compute capability. Proprietary and comple... » read more

The Future of Semiconductors: Engineering in the Convergence era
By Siemens EDA - 09 Mar, 2026 - Comments: 0

The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade. Moore’... » read more

Blog Review: Mar. 4
By Jesse Allen - 04 Mar, 2026 - Comments: 0

Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

New Challenges In Signoff
By Ed Sperling - 03 Mar, 2026 - Comments: 0

Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

Follow The AI Leader
By Brian Bailey - 03 Mar, 2026 - Comments: 0

In the 1980s, a common expression was "nobody ever got fired for buying IBM." It was considered the safe option, long after new technologies had emerged. While it may not have been the most advanced option available, it remained the safe bet. It had an established ecosystem, and it was a known quantity. But who or what is the safe bet when it comes to AI? Who has the necessary data? Who has ... » read more

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