category: System-Level Design

category: Auto, Security & Edge AI

IP Requirements Evolve For 3D Multi-Die Designs
By Madhumita Sanyal - 26 Mar, 2026 - Comments: 0

As Moore’s Law continues to slow and demand for compute density and bandwidth accelerates, the semiconductor industry is rapidly shifting from monolithic SoCs to 3D multi-die designs. While 2.5D integration has extended system scaling, it is no longer sufficient to meet the bandwidth, latency, and power requirements of AI, HPC, and advanced automotive applications. The move to true 3D multi-d... » read more

Detect, Diagnose, And Debug Using Sensors And Functional Monitoring
By Hari Mani - 26 Mar, 2026 - Comments: 1

By Hari Mani, Henrique Mendes, and Robert Wilcox Modern AI workloads drive an extremely "spiky" power profile where current demands surge to hundreds of Amps within nanoseconds, clashing with the tighter operating ranges of advanced process nodes as they push below 0.8V. This creates a physical bottleneck: the on-die power delivery network (PDN) cannot sustain the instantaneous curren... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Importance Of Hardware Security Verification In Pre-Silicon Design
By John Elliott - 26 Mar, 2026 - Comments: 0

Today’s semiconductor chips run cloud infrastructure, automotive controllers, industrial robots, and edge AI processors, so effectively the entire technology market. Engineers must now ensure that silicon itself defends against attacks, protects embedded secrets, and complies with increasingly stringent global security standards, such as ISO/SAE 21434 and the EU Cyber Resilience Act. Regulato... » read more

Shift Verification Left: AI Tools For Faster, Smarter Chip Design
By Hamid Shojaei - 26 Mar, 2026 - Comments: 0

Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report). The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-ma... » read more

Data Boom Puts Pressure On NoCs, Fabrics
By Liz Allan - 26 Mar, 2026 - Comments: 0

Key Takeaways: NoC challenges, such as wiring congestion, timing closure, and performance, must be considered in tandem with topology and placement. Topologies can be customized to meet an application’s specific data flow needs, with a system containing multiple topologies to suit different data or zones. What is challenging for one type of system, such as an SoC, switch, or AI chi... » read more

Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails
By Karen Chow - 26 Mar, 2026 - Comments: 0

By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

Removing The Accuracy And Time Tradeoff In EM Simulation
By Stephen Slater - 26 Mar, 2026 - Comments: 0

For years, electromagnetic simulation forced engineers to choose between accuracy and turnaround time. As simulation frequencies climbed beyond 60 GHz and designs became more complex, engineers could no longer avoid mesh refinement. Higher fidelity required more mesh elements in regions of high field strength. More elements produced larger sparse matrices. Larger matrices extended solve time... » read more

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

Scale AI: Engineering the Next Leap in LPDDR6 Low-Power Memory
By Keysight - 25 Mar, 2026 - Comments: 0

Scaling AI is often described as adding more GPUs and building bigger clusters, but real progress comes from system balance. As compute and throughput rise, pressure shifts to bandwidth, latency, power delivery, and thermal headroom. Memory becomes one of the earliest constraints because it sits on the critical path for feeding accelerators efficiently and consistently. In that context, JEDEC L... » read more

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