How to support workflow setup, interface resistance modeling, and RLCK extraction, positioning design teams for reliability, power efficiency, and success in next-gen device engineering.
The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive performance for AI accelerators, data centers, and mobile processors but present new extraction challenges in accurately modeling parasitic resistance and capacitance. Siemens Calibre xACT provides unified extraction tools for both front and back metal stacks—enabling precise simulation of TSV and non-Manhattan routing effects. The paper details how Calibre xACT supports workflow setup, interface resistance modeling, and RLCK extraction, positioning design teams for reliability, power efficiency, and success in next-generation device engineering.
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