Extraction Challenges of CFET and Backside Power Delivery

By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

Knowledge Centers
Entities, people and technologies explored

Can A Computer Science Student Be Taught To Design Hardware?

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.

by Liz Allan

Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

by Laura Peters

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.

by Laura Peters

Securing Hardware For The Quantum Era

Quantum computers may become a security threat as early as next year, and that threat will continue to grow over the next several years.

by Ann Mutschler

tag: BPRs

Extraction Challenges of CFET and Backside Power Delivery

Trending Articles

The Sub-2nm Paradox

AI Accelerator Testing Depends On DFT Innovations

Flash Getting Stacked High-Bandwidth Version

Chiplets Need A New Workflow

Chip Industry Week In Review

Knowledge Centers
Entities, people and technologies explored

Related Articles

Can A Computer Science Student Be Taught To Design Hardware?