Blog Review: Mar. 18

Cadence’s Jamdagni Trivedi explains the UALink Protocol Level Interface, which defines how devices exchange data and control information, and shares insights into its structure, functionality, and significance in multi-node accelerator systems.

Synopsys’ Dustin Todd argues that AI sovereignty will be defined by and built on strategic interdependence, where countries develop and retain meaningful control over the parts of the AI ecosystem that matter most to their national priorities, while partnering internationally on others.

Siemens’ Emily Yan looks at how thermal behavior in stacked architectures differs from traditional 2D monolithic SoC designs, including key challenges unique to heterogeneous integration and practical strategies for building thermal confidence into 3D-IC packaging workflows.

Keysight’s Rick Lawshae digs into the difficulty in ensuring UART security and demonstrates how fault injection can break even a highly secured UART implementation.

Arm’s Cornelius Maroa builds a HIPAA-compliant clinical note-summarization app that runs fully offline on a mobile device while retaining cloud-quality AI performance.

Imagination’s Luigi Santivetti shares a peek into the development of a GPU driver that implements the Zink translation layer to support OpenGL and OpenGL ES applications through Vulkan.

SEMI’s Samer Bahou and Jaegwan Shim share highlights from SEMICON Korea 2026, where AI was a hot topic impacting everything from memory and advanced packaging to chip design and process development.

Verification blogger Tudor Timi explores coverage extensibility in SystemVerilog, the addition of embedded covergroup inheritance in the 2023 edition, and the circumstances under which it struggles or shines.

Plus, check out the blogs featured in the latest Automotive, Security & Emerging Technologies, Test, Measurement & Analytics, and Low Power-High Performance newsletters:

Technology strategy advisor Geoff Tate looks at the benefits and challenges of orbiting servers, concluding that chip execs don’t need to start designing for space just yet.

Power architect Barry Pangrle reports on nine compelling reasons for using chiplets at the leading edge.

Rambus’ Maxim Demchenko finds that traditional Ethernet security mechanisms were not designed for the scaling and trust assumptions of next‑gen networks.

Synopsys’ Abhinav Kothiala looks at 25G Ethernet as the key enabler for edge systems to handle terabytes of sensor data and execute real-time AI inference.

Siemens EDA’s Keerthana Chelur Hithesh digs into 3D-IC ESD verification, noting that complex horizontal and vertical current flows create new failure modes that don’t exist in 2D designs.

Imagination Technologies’ Ed Plowman contends that heat and power are the main constraints for GPUs, and will drive IP, SoC integration, and architectural tradeoffs for the next decade.

Synaptics’ Vikram Gupta explains how integrating a wireless chip and a microcontroller reduces complexity and improves power management.

Cadence’s Veena Parthan outlines the benefits of localized computing facilities positioned physically close to where data is generated, including better energy efficiency and capacity utilization.

Keysight’s Doug Carson details the steps needed to secure distributed critical systems when adversaries focus on disrupting access and sabotaging with wiper malware rather than taking control.

Infineon’s Kimia Azad shows how a high-reliability package can limit switching losses, incidental device activation, and parasitic effects such as common-source inductance.

Onto Innovation’s Christopher Haire looks at new challenges in process control as specialty materials move from niche applications to mainstream products.

Siemens EDA’s Vladimir Zivkovic introduces a new methodology to create efficient manufacturing mixed-signal tests that reduce both test costs and test escapes.

Modus Test’s Jesse Ko shows how the same wafer can generate dramatically different revenue outcomes depending on test performance.

Synopsys’ Yervant Zorian and TSMC’s Sandeep Kumar Goel examine ways to fix HBM and UCIe interconnects in the field.

PDF Solutions’ Christophe Begue contends that the industry’s next competitive frontier will be won in the data layer, and not just in the fab.

Advantest’s Brent Bullock explains how to find defects that do not appear until after singulation, such as faults in chip-to-chip interconnects.

proteanTecs’ Noam Brousard highlights the importance of detecting margin degradation before it causes corruption, protecting months of training investment.

Teradyne’s Jeorge Hurtarte illustrates why multi-die packages require test techniques appropriate to each layer, including die, bridge, interposer, substrate, and stack.

Nordson EFD’s Anthony Buzzerio, along with Master Bond’s Venkat Nandivada and Rohit Ramnath, detail the benefits of precise application of biocompatible adhesives to ensure long-term sensor reliability and performance.

Rambus’ Nidish Kamath explains why the speed at which accelerators can be fed with data has become just as critical as raw compute capability.

Siemens EDA’s Harry Foster contends that the long-term objective in EDA is to let engineers spend more time on what really matters.

Arm’s Odin Shen outlines how to achieve low-latency, human-like dialogue without sending data outside the local environment.

Cadence’s Divya Chawla highlights a compact, two-pin interface that provides efficient access to debug and trace features.

Synopsys’ Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer provide a case study on adapting memory compilers and logic libraries for power-critical optical networking chips.