Chiplets 2026: Where Are We Today?

Jim Handy of Objective Analysis and Jawad Nasrullah from Palo Alto Electron kicked off last week’s Chiplet Summit with predictions about where the chiplet market is headed and why chiplets are needed to accelerate AI.

Handy noted that in the 1990s, multi-chip modules (MCMs) led to mid-’90s multi-chip packages (MCPs), and then progressed to NAND flash stacking, stacked die, big chips (e.g., Xilinx sliced FPGAs circa 2011), mixed processes (like AMD’s I/O die with core complex in the center approach), HBM with TSVs, hybrid bonding, (first used in CMOS image sensors by companies like YMTC and Sandisk), and AMD’s use of VCache. But are these all chiplets?

Figure 1. Where are chiplets used today?

For this presentation’s purposes, chiplet designs were defined as multiple chips within the same package that communicate with each other using signals optimized for in-package communications (this eliminates the first 3 in Figure 1 above).

Handy listed nine compelling reasons for using chiplets:

1. Reticle size limitations, a large design too big to fit on one chip partitioned across multiple chiplets instead.
2. Larger chips get lower yields, so using more and smaller chiplets is more economical.
3. Mask costs, large designs (near reticle) in leading-edge nodes can run in the $30 million to $50 million range for a set of masks.
4. Chiplets allow chipmakers to limit the use of expensive process nodes to only where they are advantageous.
5. They make it easier to generate more SKUs.
6. They speed up time to market with lower NRE.
7. They enable a mix different wafer technologies, like memory vs. logic, or optical.
8. Some technologies don’t shrink with process nodes (SRAM).
9. Chiplets can save power.

Figure 2. Yield vs. die area.

Xilinx’s use of multiple chiplets to produce a large FPGA is an example of how to effectively produce a larger chip, and Figure 2 shows a chart of yields using a Bose-Einstein set of curves. Large monolithic dies get the lowest yields, so chiplets are a more economically viable solution for larger applications — especially in large data-center oriented AI.

Figure 3. Large monolithic vs. small chiplets example.

Handy said that the table in Figure 3 was presented by AMD CEO Lisa Su to illustrate how a 4-Chiplet design could provide a superior solution with more total die area at only 59% of the cost. Using expensive process nodes only when there’s a clear advantage also helps to reduce costs. Figure 4 (below) shows how SRAM has effectively stopped scaling with node shrinks at around 5nm.

Figure 4. SRAM cells have stopped scaling.

Given the data plotted above, there is no reason to eat up valuable area in a leading-edge process for SRAM if, for example, the SRAM could be placed on a cheaper, older node die and connected by hybrid bonding. AMD’s Zen 5 and Zen 5c designs are examples of using different core dies and/or different numbers of core dies to generate new SKUs more economically.

HBM is an example of using different wafer technologies, combining stacked DRAM process dies with a CMOS logic base die. CMOS Image Sensors (CIS) are another example. More versions of memory are coming — MRAM, ReRAM (resistive), and FRAM (ferro-electric) increase the number of opportunities by not limiting the process for the rest of the design.

Capacitance is the nemesis of speed and low power. To the processor everything looks like a capacitor — DIMM, sockets, buses, DRAMs, and adding channels expend enormous amounts of energy to swing those signal lines. Signal lines routed on interposers have better (lower) capacitive properties.

Figure 5. Economies of scale drive down costs.

Economies of Scale Drive Down Costs. DRAM vs. NAND drove the creation of SSDs. The same phenomenon is pushing UCIe, which is a byproduct of increasing scale and reducing I/O design cost.

Figure 6. Nvidia’s data center revenues have skyrocketed.

Figure 7. Is all this AI spending sustainable?

Nvidia’s data center revenues have skyrocketed, and hyperscaler capital expenditures soared past $70B in 2025, about double those in 2024. CapEx is also an higher percentage of hyperscaler revenue for AI spending, roughly doubling in terms of revenue percentages over the past five years.

Handy noted that chiplets don’t create new markets, but they are fueling AI. Chiplets are an enabling technology, and he expects that hybrid bonding is going to be a really big thing.

The presentation wrapped up with a chiplet forecast of $600B chiplet for 2031, about equal to 2025’s total semiconductor revenue. So chiplet market penetration will continue, driven by the large capital expenditures for AI systems.

Figure 8. Chiplet forecast.

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