category: System-Level Design

category: IoT, Security & Automotive

RTL Architect: Simply Better RTL
By Synopsys - 27 May, 2020 - Comments: 0

Electronic devices play a key role in society. They connect us to one another through voice, video and chat. They entertain, educate, protect and heal us in new and ever-expanding ways. They have changed the way we work, live and play. Silicon chips are the fast beating heart (2 to 3 billion beats per second) of these devices. For decades, the relentless advancements in semiconductor process te... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2020 - Comments: 0

Mentor's Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences. Cadence's Paul McLellan explains the history of neural networks and how we've been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated i... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 May, 2020 - Comments: 0

Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2020 - Comments: 0

Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Rising Packaging Complexity
By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

Blog Review: May 13
By Jesse Allen - 13 May, 2020 - Comments: 0

Mentor's Neil Johnson considers when in a project certain verification methods should be deployed and the relative impact of techniques at a given point in subsystem design. Cadence's Paul McLellan looks back at the development of mobile standards with 2G, GSM, and the transition to all-digital transmission. Synopsys' Taylor Armerding highlights five online courses to boost your software ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 May, 2020 - Comments: 0

Tools & IP Ansys' RedHawk-SC multiphysics signoff software was certified for all TSMC advanced process technologies, including N16, N12, N7, N6 and N5. The certification includes extraction, power integrity and reliability, signal electromigration (EM) and thermal reliability analysis and statistical EM budgeting analysis. Aldec launched a new FPGA accelerator board for high performance... » read more

Blog Review: May 6
By Jesse Allen - 06 May, 2020 - Comments: 0

In a blog for Arm, Javier Fernandez-Marques of Oxford University digs into how to make the best use of quantized neural network models and why it's so important to consider what algorithms will be running when deciding which model architecture to implement, and which quantization strategy to adopt for the model. Synopsys' Taylor Armerding explains why, with a largely remote workforce, it may... » read more

Key Drivers In New Chip Industry Outlook
By Ed Sperling - 04 May, 2020 - Comments: 0

How well the semiconductor industry fares over the next 12 to 24 months depends upon the evolution of a virus. That alone will determine the correct model for an economic rebound — V, U, extended U, or maybe even a double U. But what's also becoming clear is those models don't apply uniformly to all sectors or sub-sectors of the semiconductor industry. Looked at as a whole, the entire indu... » read more

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