category: System-Level Design

category: Auto, Security & Edge AI

Aging Analysis Common Model Interface Gains Momentum
By Greg Curtis - 25 Mar, 2021 - Comments: 0

By Greg Curtis, Ahmed Ramadan, Ninad Pimparkar, and Jung-Suk Goo In February 2019, Siemens EDA wrote an article1 entitled “The Time Is Now for a Common Model Interface”. Since that time, we have continued to see increasing demand for aging analysis, not only in the traditional automotive space, but also in other areas of technology design, such as mobile communication and IoT application... » read more

Processing With FPGAs On Mars
By Farhad Fallahlalehzari - 25 Mar, 2021 - Comments: 0

Tasked with finding life in the form of microorganisms, the rover Perseverance landed on Mars at about 04:00 EST on February 18, 2021. The rover has multiple sensors and cameras to collect as much data as possible and, due to the volume of live data being recorded and the long data transmission time from Mars to Earth, a powerful processing system is essential. However, whereas early Mars ro... » read more

Exercising State Machines with Command Sequences
By Siemens EDA - 24 Mar, 2021 - Comments: 0

Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design. In other cases, the state machine... » read more

A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing
By Codasip - 24 Mar, 2021 - Comments: 0

This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to co... » read more

Overcoming Next-Generation AESA Radar Design Challenges
By Cadence - 24 Mar, 2021 - Comments: 0

Phased array antennas were first used in military radar systems to scan the radar beam quickly across the sky to detect planes and missiles. These systems are becoming popular for a variety of applications and new active electronically scanned arrays (AESAs) are being used for radar systems in satellites and unmanned aerial vehicles. As these systems are deployed in new and novel ways, size and... » read more

Blog Review: March 24
By Jesse Allen - 24 Mar, 2021 - Comments: 0

Arm's Brian Cline points to a project with GlobalFoundries to demonstrate the feasibility and readiness of high-density, face-to-face, wafer-bonded 3D stacking technologies for high performance, energy-efficient designs. Synopsys' Taylor Armerding warns that while supply chain security risks aren't new, the recent SolarWinds breach should make everyone pay much more attention to dependencies... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Mar, 2021 - Comments: 0

Qualcomm finalized its acquisition of data center chip startup Nuvia with a price of $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia’s technology wo... » read more

Blog Review: March 17
By Jesse Allen - 17 Mar, 2021 - Comments: 0

Synopsys' Chris Clark considers the growing number of automotive sensors and the cost/performance tradeoffs between edge computing capability, sensor fusion, sensor degradation, monitoring, and the maintenance of the software over the lifespan of a vehicle. Cadence's Paul McLellan checks out how the process of loading the bootstrap into memory has changed over the years, from hand-entered on... » read more

An Insider’s View Of Verifying Custom RISC-V Processor Cores
By Shubhodeep Roy Choudhury - 15 Mar, 2021 - Comments: 0

By Shubhodeep Roy Choudhury, Valtrix Systems, and Lee Moore, Imperas Software Supporting images courtesy of Bill McSpadden, Seagate Technology This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V proce... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Mar, 2021 - Comments: 0

Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

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