category: System-Level Design

category: IoT, Security & Automotive

Microsoft Accelerates DRC With Shift-Left Verification
By Siemens EDA - 30 Jan, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Chiplets Still A Challenge With UCIe 2.0
By Brian Bailey - 30 Jan, 2025 - Comments: 0

Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires. Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable s... » read more

Design Customization Puts Heavy Burden On Verification
By Ann Mutschler - 30 Jan, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor Engineering sat down with a panel of experts, including Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director for verification software product management at Cad... » read more

Fast Monte Carlo Simulations For Timing Variation Analysis
By Vinod Khera - 30 Jan, 2025 - Comments: 0

Process variations and device mismatches profoundly affect the latest ultra-small geometrical processes. Complexity creates additional factors that impact device manufacturing variability, which in turn impact overall yield. Monte Carlo (MC) simulations use repeated random sampling to relate process variations to circuit performance and functionality, thus determining how they impact yield. How... » read more

Blog Review: Jan. 29
By Jesse Allen - 29 Jan, 2025 - Comments: 0

Cadence's Reela Samuel looks beyond silicon to new semiconductor materials under development and the particular applications for gallium nitride, silicon carbide, indium phosphide, glass, and diamond. Siemens' Kyle Fraunfelter and Melville Bryant find that lean approaches alone cannot address the increasingly complex sustainability challenges of semiconductor manufacturing and call for the e... » read more

The Digital Twin Technology Applied to 6G Communication
By Keysight - 29 Jan, 2025 - Comments: 0

This paper provides a comprehensive overview of digital twin technology, starting with its definition as a dynamic virtual representation of physical systems. Furthermore, we distinguish between simulators and digital twins, highlighting their key differences and characteristics particularly related to the interactions with real-time data. The paper also delves into the evolution of digital ... » read more

What IoMT Really Stands For
By Brad Jolly - 27 Jan, 2025 - Comments: 0

The basic goals of engineering include the achievement of a product’s purpose, safety, cost, manufacturability, and supportability, among other things. For internet of things (IoT) applications, much of the essential purpose relates to wireless communications that untether communication from wires and cables. This is especially true of the rapidly growing internet of medical things (IoMT), wh... » read more

Livelocks And Deadlocks In NoCs
By Ed Sperling - 22 Jan, 2025 - Comments: 0

Devices that are stuck in a specific state, or which appear to be making progress even though they are not, are common problems in complex systems. Processing elements need to fetch data they don't have from routers may be frozen out by other processors, a problem that is exacerbated by common bus protocols. Ashish Darbari, CEO of Axiomise, talks about how to identify potential bottlenecks, why... » read more

Blog Review: Jan. 22
By Jesse Allen - 22 Jan, 2025 - Comments: 0

Cadence's David Shin provides an overview of the eUSB2V2 specification, which scales up to 4.8Gbps of data rate and provides the flexibility to configure either asymmetrical or symmetrical links depending on the intended application. Siemens EDA's Spencer Acain highlights the key role of AI in semiconductor testing, including the addition of analytical AI in DFT tools and how applying machin... » read more

Blog Review: Jan. 15
By Jesse Allen - 15 Jan, 2025 - Comments: 0

Siemens EDA's Stephen V. Chavez argues that the placement of decoupling capacitors on a PCB can make or break a design's power delivery system and provides some best practices and design considerations, such as ensuring even distribution on a board rather than crowding them around chips. Synopsys' Stelios Diamantidis predicts that in 2025, AI agents will begin collaborating with other AI age... » read more

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