category: System-Level Design

category: IoT, Security & Automotive

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization
By Cadence - 25 Sep, 2024 - Comments: 0

Abstract Over the past few decades, a lot of details have been worked out in power distribution network design, simulation and measurement. We have well-established PDN design procedures both in the frequency and time domains, we have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior, and we also have fre... » read more

Accelerate Your Digital Transformation with ADS Python Automation
By Keysight - 25 Sep, 2024 - Comments: 0

Three automation use cases for expanded Keysight ADS Python APIs transforming modern RF and high-speed design include: Use Case 1 – Python for Personal Productivity: One advantage of Python is its easy accessibility to entry-level programmers.  Python is an interpreted language that is free and widely supported on Windows and Linux, is expandable to many domains with plug-ins, and allows... » read more

UMI Can Scale the Memory Wall
By Eliyan - 25 Sep, 2024 - Comments: 0

While the improvements in processor performance to enable the incredible compute requirements of applications like Chat-GPT get all the headlines, a not-so-new phenomenon known as the memory wall risks negating those advancements. Indeed, it has been clearly demonstrated that as CPU/GPU performance increases, wait time for memory also increases, preventing full utilization of the processors. ... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2024 - Comments: 0

Cadence’s Mamta Rana digs into how PCIe 6.1 ECN builds on the FLIT-based architecture introduced in PCIe 6.0, further optimizing flow control mechanisms to handle increased data rates and improved efficiency but making verification of shared credit updates essential. Siemens’ Nicolae Tusinschi provides a primer on formal verification, including what makes it different from simulation, pr... » read more

What Comes After HBM For Chiplets
By Brian Bailey - 18 Sep, 2024 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss what will trigger the creation of a commercial chiplet marketplace, and what those chiplet-based designs will look like, with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technology at Marvell; Kevin Yee, senior director of IP and ecosystem marketing at Samsung; Sailesh Kumar, CEO of Baya Systems; and Tanuja... » read more

Blog Review: Sept. 18
By Jesse Allen - 18 Sep, 2024 - Comments: 0

Siemens’ Kyle Fraunfelter explores the similarities between hurricane forecasting and semiconductor manufacturing to argue for the value of integrating real-time wafer fabrication measurements into the digital twin models used to simulate the semiconductor fabrication process. Cadence’s Rohini Kollipara introduces Display Stream Compression (DSC), which can enable higher resolutions and ... » read more

Blog Review: Sept. 11
By Jesse Allen - 11 Sep, 2024 - Comments: 0

Cadence's Neha Joshi introduces the IEEE 1801 standard, also known as UPF (Unified Power Format), which offers a uniform framework for defining power domains, power states, and power intent to ensure consistency across diverse tools and phases of the design process. Siemens' John McMillan warns that known good die may not behave the same in 3D-ICs as they do standalone and suggests that mult... » read more

New AI Processors Architectures Balance Speed With Efficiency
By Ed Sperling - 04 Sep, 2024 - Comments: 1

Leading AI systems designs are migrating away from building the fastest AI processor possible, adopting a more balanced approach that involves highly specialized, heterogeneous compute elements, faster data movement, and significantly lower power. Part of this shift revolves around the adoption of chiplets in 2.5D/3.5D packages, which enable greater customization for different workloads and ... » read more

Blog Review: Sept. 4
By Jesse Allen - 04 Sep, 2024 - Comments: 0

Synopsys' Jyotika Athavale and Randy Fish sit down with Google's Rama Govindaraju and Microsoft's Robert S. Chappell to discuss silent data corruption and why a solution will require chip designers and manufacturers, software and hardware engineers, vendors, and anyone involved in computer data to collaborate and take the issue seriously. Siemens' Karen Chow and Joel Mercier explain the rela... » read more

Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies
By Ramin Farjadrad - 29 Aug, 2024 - Comments: 0

In designing multi-die systems-in-package, with or without chiplets, it is easy to think of the interconnect between dies as simply analogous to the interconnect between functional blocks on a single die. But this analogy can lead architects and designers into a blind alley from which it becomes impossible to meet system performance and power requirements. The reason lies in fundamental differe... » read more

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