category: System-Level Design

category: IoT, Security & Automotive

UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall
By Ramin Farjadrad - 14 Oct, 2024 - Comments: 0

With the Open Compute Project (OCP) Summit upon us, it’s an appropriate time to talk about chiplet interconnect (in fact the 2024 OCP Summit has a whole day dedicated to the multi-die topic, on October 17). Of particular interest is the Bunch of Wires (BoW) interconnect specification that continues to evolve. At OCP there will be an update and working group looking at version 2.1 of BoW. (... » read more

Blog Review: Oct. 9
By Liz Allan - 09 Oct, 2024 - Comments: 0

Siemens’ Stephen Chavez looks at the key benefits and challenges to achieving a successful ECAD-MCAD collaboration. Cadence’s Nayan Gaywala shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform, using a dual-core design mapped to a KC705 platform as an example. Synopsys’ Vincent van der Leest digs into SRAM PUFs and their ... » read more

EDA And IP Revenue Grow, But Markets Are Shifting
By Ed Sperling - 07 Oct, 2024 - Comments: 0

EDA and IP revenue grew 18.2% worldwide to $4.69 billion in Q2, year-over-year, with all product categories and regions reporting increases, but a drill down into the numbers shows some new pockets of growth and weakness The Asia/Pacific region exhibited strong growth once again, but the dynamics in that market have changed significantly. China is no longer the primary revenue generator for ... » read more

Partitioning In The Chiplet Era
By Ann Mutschler - 03 Oct, 2024 - Comments: 0

The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs. Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be short... » read more

Working With Chiplets
By Ed Sperling - 02 Oct, 2024 - Comments: 0

The usual method of migrating to the next process node to cram more features onto a piece of silicon no longer works. It's too expensive, and too limited for most applications. The path forward is now heterogeneous chiplets targeted at specific markets, and while logic will continue to scale, other features are being separated out into chiplets developed using different process technologies. Th... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Corner-Case Bug Hunting for RISC-V
By Ashish Darbari - 30 Sep, 2024 - Comments: 0

By Ashish Darbari and Ia Tsomaia RISC-V continues to make headlines worldwide, but verification continues to be challenging. The findings of the Wilson Research Report, 2022 (see figure 1) make the trends in verification clear. We presented these in a keynote talk titled, "Future is Formal," at the recent DVCon India event. One thing is quite apparent: whether you are using directed tests... » read more

Barriers To Chiplet Sockets
By Brian Bailey - 30 Sep, 2024 - Comments: 0

Experts At The Table: Demand for chiplets is growing, but debate continues about whether standards and general-purpose chiplets will kick-start the commercialization boom, or whether success will come through customization of those chiplets. Semiconductor Engineeering sat down to discuss these and other related issues with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technol... » read more

Accelerating Reset Domain Crossing Verification With Data Analytics Techniques
By Reetika - 26 Sep, 2024 - Comments: 0

By Reetika and Sulabh Kumar Khare As the complexity of integrated circuit (IC) designs continues to rise, the task of verifying these designs has become increasingly challenging. The pace of this growth is staggering, with design complexity doubling roughly every 20 months. This exponential increase places immense pressure on verification processes, which must keep up to ensure that these so... » read more

PAM4: Pulse Amplitude Modulation Explained
By Ben Miller - 26 Sep, 2024 - Comments: 0

Pulse amplitude modulation (PAM) is already a widely adopted technology in high-speed digital communications. But to understand why it has become ubiquitous in serial data standards, you first must understand the market forces driving the data networking industry. In this article, I will explore PAM4 in-depth, from its benefits and potential tradeoffs to why it was an essential innovation that ... » read more

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