category: System-Level Design

category: Auto, Security & Edge AI

New Challenges In Signoff
By Ed Sperling - 03 Mar, 2026 - Comments: 0

Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

Follow The AI Leader
By Brian Bailey - 03 Mar, 2026 - Comments: 0

In the 1980s, a common expression was "nobody ever got fired for buying IBM." It was considered the safe option, long after new technologies had emerged. While it may not have been the most advanced option available, it remained the safe bet. It had an established ecosystem, and it was a known quantity. But who or what is the safe bet when it comes to AI? Who has the necessary data? Who has ... » read more

Accelerate Your IP Selection With Smart Solido Library Profiler
By Siemens EDA - 02 Mar, 2026 - Comments: 0

This white paper discusses the IP selection process, its requirements, challenges, and proposed solutions. The process of choosing cell IP libraries for integrated circuit (IC) design is a slow and complicated process due to the inconsistencies and complexities of library files, particularly across sources, technology nodes, and variants. Manual methods to achieve IP selection not only consumes... » read more

How IP Subsystems For Chiplets Will Unlock Your Next Wave Of Innovation
By Robert Kruger - 26 Feb, 2026 - Comments: 0

After many years of hope, promises, and commercial challenges, a robust environment that supports multi-die design is now taking shape. These events represent a sea of change for semiconductor design and manufacturing when compared to the traditional single-die monolithic design approach. Moore’s Law drove these original and substantial monolithic design accomplishments. But the massive requi... » read more

AI Energy Gap And Chiplets: Why Data Movement Matters
By Ashley Stevens - 26 Feb, 2026 - Comments: 0

At the recent Chiplet Summit 2026 preconference tutorial, the panel session, “Best Way to Make Chiplets Work,” brought together leaders from across the semiconductor ecosystem to tackle one of the most pressing challenges in advanced system design: how do we make heterogeneous, multi-die systems operate as a cohesive, energy-efficient whole for AI? While much discussion focused on st... » read more

Using Data And AI More Effectively In EDA
By Brian Bailey - 26 Feb, 2026 - Comments: 0

Key Takeaways The data being produced by EDA tools tends to be for human consumption and has weak semantics. Agents are attempting to create actionable information from unstructured data. The Model Context Protocol may provide AI with access to better data. Semiconductor design generates a lot of data, but how much of that is useful or currently being used by AI tools? And h... » read more

AI Starting To Simplify Design Of Programmable Logic
By Liz Allan - 26 Feb, 2026 - Comments: 0

Key Takeaways AI/ML and agentic tools are getting better at helping design and compile FPGAs, but downstream programming is slower to benefit. FPGAs historically have been designed using Verilog or VHDL, but higher-level languages could push more intelligence into compilers. ML tools can also help with mixed-signal co-design by automatically tuning DSP algorithms based on analog simu... » read more

An Integrated Workflow For Circuit Design, Simulation, And Functional Safety Analysis
By Daniel Zhang - 26 Feb, 2026 - Comments: 0

By Daniel Zhang and Claudius Jordan Functional safety analysis is a crucial step in the development of safety-critical systems. It ensures that the system-under-development meets its defined safety requirements and functions safely under both nominal and fault conditions. In the event of a failure, the system must respond appropriately to mitigate the risk of safety hazards that could potent... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

Data Center Digital Twins: How Simulation Improves Design And Performance
By Veena Parthan - 26 Feb, 2026 - Comments: 0

Data center digital twins are transforming data center design from assumption-based planning to physics-backed simulation—well before the first rack is deployed. By combining physics simulations with real operational data, a data center digital twin enables teams to predict performance, reduce risk, and optimize capacity with measurable confidence. As power densities rise from AI and hype... » read more

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