EDA On Cloud Presents Unique Challenges


Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

Blog Review: March 30


Ansys' Shawn Carpenter takes a look at the continuing impact of potential interference with aircraft's radar altimeters on the roll out of the 5G C-band and the testing that will be needed to enable 5G C-band service towers to begin operating near airports by July. Siemens' Harry Foster points to an increase in the number of engineers working on automotive ASIC projects and the growing compl... » read more

Week In Review: Design, Low Power


Design services firm SemiFive acquired Analog Bits, a provider of low-power mixed-signal IP. Analog Bits' portfolio includes precision clocking macros, I/Os, SerDes, and sensors to monitor PVT. It was founded in 1995 and based in Sunnyvale, California. “Analog Bits has a solid track record of developing and delivering differentiated and high-quality mixed signal IP addressing multiple market ... » read more

UCIe: Marketing Ruins It Again


You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

Incremental Design Breakdown


For the past two decades, most designs have been incremental in nature. They heavily leveraged IP used in previous designs, and that IP often was developed by third parties. But there are growing problems with that methodology, especially at advanced nodes where back-end issues and the impact of 'shift left' are reducing the savings from reuse. The value of IP reuse has been well established... » read more

Autonomous Design Automation: How Far Are We?


The year is 2009, during the Design Automation Conference (DAC) at a press dinner in a posh little restaurant in San Francisco’s Civic Center. About two glasses of red wine in, one of the journalists challenges the table: “So, how far away are we from the black box that we feed with our design requirements and it produces the design that we send to the foundry?” We discussed all the indus... » read more

Overcoming The Growing Challenge Of Dynamic IR-Drop


IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits swi... » read more

How To Justify A Data Center


The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud. Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but which no one was serious about ... » read more

The Value Of RF Harmonic Balance Analyses For Analog Verification


By Pradeep Thiagarajan and Scott Guyton The world we live in is intricately connected by electronic systems that are expected to function flawlessly to satisfy consumer needs. Functionality violations beyond certain tolerance levels are frowned upon and negatively impact the quality level of products. These systems are required to function accurately, in tandem with other interdependent syst... » read more

Improve Your Verification Methodology: Hunt Bugs Flying In Squadrons


After analyzing bugs on several generations of CPUs, I came to the conclusion that “bugs fly in squadrons.” In other words, when a bug is found in a given area of the design, the probability that there are other bugs with similar conditions, in the same area of the design, is quite high. Processor bugs don’t fly alone Finding a CPU bug is always satisfying, however it should not be an e... » read more

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