category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Feb. 1
By Jesse Allen - 01 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster explores trends in low power design techniques for ICs and ASICs, with 72% of design projects reported actively managing power. Synopsys' Charlie Matar, Rita Horner, and Pawini Mahajan look at the concept of reliability, availability, and serviceability (RAS) in the context of high-performance computing SoC designs and how it can be supported with silicon lifecycle... » read more

Importance Of Qualifying IP Revisions
By Siddharth Ravikumar - 30 Jan, 2023 - Comments: 0

Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

A New Year’s Wish
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Every year I run a predictions article. It is a mashup of ideas from many people within the industry, and while many predictions are somewhat self-serving, there are other which come more from the heart — or perhaps they are dreams rather than expectations. I see hope in some of those, particularly the ones that look toward sustainability within our industry, and of our industry. Just like... » read more

The Importance Of Phase-Coherent RF Signal
By TJ Cartwright - 26 Jan, 2023 - Comments: 0

As the number of higher-throughput applications grows, so does the need for wider bandwidth and network coverage in wireless systems. Given limited spectrum allocation, wireless communication engineers must look for ways to improve spectral efficiency and the signal-to-noise ratio (SNR) of systems. Multiple-input / multiple-output (MIMO) and beamforming can help RF designers achieve diversity, ... » read more

IEDM: TSMC N3 Details
By Paul McLellan - 26 Jan, 2023 - Comments: 0

I attended IEDM in San Francisco in December. There were two presentations about TSMC's N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the second generation) is called N3E. The two papers were: Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond A 3nm CMOS FinFl... » read more

Benefits Of A Silicon-Proven 800G Ethernet Solution For High-Performance Computing
By Madhumita Sanyal - 26 Jan, 2023 - Comments: 0

The evolution of high-speed Ethernet began in 2014 when Arista, Broadcom, Microsoft, Mellanox and Google formed the Ethernet Consortium, now called the “Ethernet Technology Consortium.” Since then, the technology has been adopted by more than 45 members. The push for 200G, then 400G, and now 800G Ethernet is driven by the insatiable need to process and transmit high-performance workloads in... » read more

Power Issues Causing More Respins At 7nm And Below
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

5 Takeaways From The RISC-V Summit
By Lauranne Choquin - 26 Jan, 2023 - Comments: 0

After an intense week at the 2022 RISC-V Summit in San Jose, California, I am fueled with energy and positive thoughts. I had plenty of time to reflect on the event, which was unique in many ways. A lot happened in a few days for us at Codasip as well as for the wider RISC-V community, and here are 5 things I will remember from this conference. 1. RISC-V is inevitable If you have read our a... » read more

CXL Picks Up Steam In Data Centers
By Marie C. Baca - 26 Jan, 2023 - Comments: 0

CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

The QA Exchange Deck In Solido Crosscheck Enables An IP Qualification Handshake
By Siemens EDA - 26 Jan, 2023 - Comments: 0

This paper describes how the QA exchange deck in Siemens EDA’s Solido Crosscheck software can be used to capture and exchange IP qualification requirements. It shows how the QA exchange deck can be used as part of the IP validation framework in Solido Crosscheck to provide an IP signoff handshake between IP suppliers and integrators. To read more, click here. » read more

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