Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking


Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows that require correct connectivity for valid results. The Calibre nmLVS Recon tool targets essential and relevant early-stage circuit verification pain points, such as electrical rule checking (ERC) ... » read more

Smart Devices Enabled To Efficiently Communicate, Sense, Hear, Act And Interact With User


The latest advancements in embedded systems and communication and sensing technology have led to the increasing development of smart applications. This has been a continuously evolving process, involving either the creation of completely new solutions or the rapid transformation of existing ones into corresponding highly smart environments. The main driving forces of the smart transformation ha... » read more

Blog Review: Feb. 22


Siemens EDA's Harry Foster observes that the FPGA market continues to go through a similar complexity curve that the IC/ASIC market experienced in the early and mid-2000 timeframe. Synopsys' Mitch Heins explores the benefits of heterogeneous integration of lasers and active gain elements in a silicon-based photonic IC, including reduced system costs, size, weight, and power along with improv... » read more

Advanced Modulation And Coding Challenges


Demands for a connected world with instant data access continue to drive data center transceiver innovation. 100 gigabit Ethernet (GE) data transmission is in production and will continue to evolve. But 100GE speeds aren’t fast enough to support the expected surge in connected devices and the applications they will run, opening the door for 400GE. Non-return-to-zero (NRZ) and four-level pulse... » read more

Efficient Verification Of RISC-V Processors


For some time, application-specific instruction processors (ASIPs) have been developed for specialized applications. These have required multi-disciplinary teams with sufficient expertise to develop the instruction set, microarchitecture, and software toolchain. Few companies have had the right combination of skills to develop ASIPs so relatively few have been developed. With the advent of R... » read more

Best Practices For Cybersecurity-Aware SoC Development With ISO 21434


The growth of electronics in cars is exposing a new vector for cyberattacks on owners and automotive companies’ reputations. The potential human cost of an attack on the car’s electronics is driving urgency in the adoption of cybersecurity-aware practices, from OEMs and Tier 1s to every component supplier in the automotive industry. The standard “ISO/SAE 21434:2021 Road vehicles — Cyber... » read more

Blog Review: Feb. 15


Siemens EDA's Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production, as well as whether safety critical development processes yield higher quality in terms of preventing bugs and achieving silicon success. Synopsys' Shankar Krishnamoorthy finds that the rapid progress of machine learning models is driving demand for more domain-speci... » read more

Week In Review: Design, Low Power


Arm is heading for an IPO this year, with plans "fairly well developed and underway now," CEO Rene Haas told Reuters. Arm reported fiscal Q3 revenue of $746 million, up 28% compared with the same period in 2021, setting the stage for a public offering. The company noted it had double- or triple-revenue increases in automotive, consumer, infrastructure, and IoT. The Si2 Compact Model Coalit... » read more

Blog Review: Feb. 8


Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Week in Review: Design, Low Power


Intel discontinued its Pathfinder for RISC-V program, according to numerous reports. The program provided a pre-silicon development environment to support IP selection and early-stage software development using Intel FPGA and simulator platforms. "Since Intel will not be providing any additional releases or bug fixes, we encourage you to promptly transition to third-party RISC-V software tools ... » read more

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