Week In Review: Design, Low Power

Arm, Intel DTCO for 18A process; 30 billion gate emulation; passive device synthesis; stackable CAMM.


Arm and Intel Foundry Services inked a multi-generation agreement to enable chip designers to build Arm-based SoCs on the Intel 18A process. The initial focus is mobile SoC designs, but the deal allows for potential expansion into automotive, IoT, data center, aerospace, and government applications. IFS and Arm will undertake design technology co-optimization (DTCO) to optimize chip design and process technologies and improve PPAC for Arm cores targeting Intel 18A process technology. They will develop a mobile reference design.

Additionally, Rambus joined the Intel Foundry Services Accelerator IP Alliance to provide advanced security and interface IP solutions optimized for performance, power, area and security for Intel process and packaging technologies.

Creating chiplets with as much flexibility as possible has captured the imagination of the semiconductor ecosystem, but how heterogeneous integration of chiplets from different foundries will play out remains unclear. Along with ensuring chiplets can communicate with each other, communication between chip/chiplet/system architects, the packaging technology teams, and the ASIC design teams to determine what IP is available in different technologies is a significant aspect of chiplet design.

Oak Ridge National Laboratory and the National Oceanic and Atmospheric Administration are launching a new supercomputer dedicated to climate science research. Gaea C5 is an HPE Cray machine with over 10 petaflops of peak theoretical performance, giving it almost double the power of the combined two previous systems deployed by ORNL’s National Climate-Computing Research Center.

JEDEC is expanding its CAMM standardization efforts to include stackable CAMMs and support of LPDDR5. Stackable CAMM splits the dual-channel CAMM connector lengthwise into two single-channel CAMM connectors, with one DDR5 memory channel per connector. Two single-channel connectors can reside on the same motherboard in place of one dual-channel connector, providing system configuration options.

Tools & products

Synopsys launched its latest emulation system, ZeBu Server 5, which uses AMD Virtex UltraScale+ VU19P FPGAs. The company said it supports up to 30 billion gates capacity with 2x higher throughput, 2x better emulation performance, and less than half of the power consumption compared to the previous generation.

Cadence unveiled a passive device synthesis and optimization technology. EMX Designer can provide design rule check (DRC)-clean parametric cells (PCells) and accurate electromagnetic models of passive devices, such as inductors, transformers, and T-coils, for any foundry process node down to 3nm and is integrated with the Virtuoso ADE product suite.

Renesas Electronics started sampling its first microcontroller (MCU) based on 22nm process technology. An extension the RA family of 32-bit Arm Cortex-M MCUs, it includes Bluetooth 5.3 Low Energy with the integration of a software-defined radio (SDR).

While there has been much discussion about 3D designs, there are multiple interpretations about what 3D entails. This is more than just semantics, however, because each packaging option requires different design approaches and technologies. And as chips push into the realm of real 3D-ICs, stacking logic or memory on top of logic, they become much more challenging to design, manufacture, and ultimately yield and test.

Rapid Silicon launched an AI-based tool with advanced conversational features and code autocompletion capabilities dedicated to FPGAs. RapidGPT aims to reduce the time needed for FPGA designers to become productive with new tools and platforms by providing contextual suggestions based on their code, removing errors, and streamlining the code writing process.

VeriSilicon uncorked new super resolution display IP to increase the resolution and quality of low-resolution video sources.

IC Manage and Library Technologies teamed up to enable horizontal CPU scaling in the cloud and reduce library characterization runtimes.

Silicon photonics is undergoing a resurgence as traditional approaches for reducing power and heat become more difficult and expensive. However, photonics is extremely complex from a technology standpoint: signals drift, they are modulated with heat, and structures like interconnects and waveguides are very different from traditional electrical designs. From a skills standpoint, there is a shortage of expertise at all levels, and one that may be exacerbated by talent shortages in other parts of the chip industry.


Axelera AI selected Ansys simulation software as part of a two-step, top-down flow to validate floorplan quality and IR drop for digital power integrity signoff of its high-performance Metis AI Processing Unit.

ASICLAND licensed Arteris IP’s FlexNoC with Automotive ASIL B and AI options. It will be used for the main system bus for automotive and AI SoCs for a variety of applications.

Kudan and Visionary.ai joined Cadence’s Tensilica software partner ecosystem, adding Kudan’s simultaneous localization and mapping (SLAM) and Visionary.ai’s AI image signal processor (ISP) software solutions for Tensilica Vision and AI DSPs.

Over the past decade, silicon interposer technology has evolved from a simple interconnect into a critical enabler for heterogeneous integration. It is not uncommon to see a heterogeneous integrated design on interposers with area above 2,000 mm², drawing 600 watts of power for the system, and requiring very high I/O bandwidth. With that kind of power, thermal integrity is now a first-order concern, and one that makes it much more difficult to sign-off on schedule with high confidence.

Research notes

Researchers at the National Institute of Standards and Technology (NIST) developed chip-scale devices for simultaneously manipulating the color, focus, direction of travel, and polarization of multiple beams of laser light. The single-chip design combines integrated photonic circuits and an optical metasurface to perform the work of 36 optical components. It could be used to create portable sensors that could measure such fundamental quantities as rotation, acceleration, time, and magnetic fields with high accuracy outside a laboratory.

Fluxonium qubits could form the basis for new fault-tolerant quantum processors, suggest researchers from Lawrence Berkeley National Laboratory, University of California Berkeley, and Yale University. A type of superconducting qubit, the fluxonium circuit is composed of three elements: a capacitor, a Josephson Junction, and a superinductor, which helps suppress magnetic flux noise. Key to the fluxonium qubit’s potential is its high anharmonicity, which refers to the difference between relevant transition frequencies in a qubit. This enables better qubit control because there’s less overlap between the frequencies that control the qubits and those that drive any given qubit to higher energy levels. The qubit also appears to have long coherence times.

Engineers at Duke University produced fully recyclable printed electronics that replace the use of chemicals with water in the fabrication process. The devices use three carbon-based inks: semiconducting carbon nanotubes, conductive graphene, and insulating nanocellulose. To enable using water to print the carbon nanotubes involves rinsing the device with water, drying in relatively low heat, and printing on again. Nearly 100% of the carbon nanotubes and graphene used in printing can be recovered and reused in the same process, while the nanocellulose can be recycled or biodegraded like paper.

FinFETs are being supplanted by gate-all-around (GAA) starting at 3nm. But the industry still does not know much about these devices, or how significant some of the issues will be long-term. As with any new device, the first generation is a learning vehicle and improvement are made over time.

Upcoming events

  • Design, Automation and Test in Europe Conference (DATE 2023) — April 17-19 (Antwerp, Belgium)
  • CadenceLIVE Silicon Valley 2023 — April 19-20 (Santa Clara, CA)
  • TSMC 2023 Technology Symposium — April 26 (Santa Clara, CA)
  • The Impact of New Regulations on the Semiconductor Design Ecosystem (hosted by ESD Alliance) — April 26 (San Jose, CA)
  • COMSOL Day: Semiconductor Manufacturing – April 27 (Online)
  • IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – May 1-4 (San Jose, CA)
  • Women in Semiconductor: WIS 2023 – May 1 (Saratoga Springs, NY)
  • ITF World 2023 – May 16-17 (Antwerp, Belgium)
  • Annual ESD Alliance Membership Meeting & CEO Outlook – May 18 (Santa Clara, CA)
  • More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • True 3D Is Much Tougher Than 2.5D
  • The Race Toward Mixed-Foundry Chiplets
  • Managing EDA’s Rapid Growth Expectations
  • Thermal Integrity Challenges Grow In 2.5D
  • What Designers Need To Know About GAA
  • Transitioning To Photonics

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