category: System-Level Design

category: Auto, Security & Edge AI

Week In Review: Design, Low Power
By Jesse Allen - 13 Jan, 2023 - Comments: 0

With funding from the Semiconductor Research Corporation, a group of 10 universities is banding together to create the Processing with Intelligent Storage and Memory center, or PRISM, led by University of California San Diego. The $50.5 million PRISM center will focus on four different themes: novel memory and storage devices and circuits; next generation architectures; systems and software; an... » read more

Blog Review: Jan. 11
By Jesse Allen - 11 Jan, 2023 - Comments: 0

Cadence's Veena Parthan explains why in CFD, understanding the consequences of choices regarding the computational mesh is essential for generating high-fidelity simulation results. Synopsys' Chris Clark shares key considerations and questions to factor in when developing solutions for software-defined vehicles that must meet safety, security, reliability, and quality standards. Siemens E... » read more

Automated Late Stage Timing-Aware Dynamic Voltage Drop ECO
By Manoj Chacko - 09 Jan, 2023 - Comments: 0

One of the never-ending frustrations for electrical engineers is having to deal with counterproductive real-world effects that they wish would just go away. Examples include switch bounce, metastability, and contact resistance. For IC designers, dynamic voltage drop (DVD), also known as IR drop, is one of those unfortunate facts of the profession. There’s no way to avoid it; every trace and w... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 06 Jan, 2023 - Comments: 0

Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google's director of engineering for the Android Platform Programming Languages, noted that Android currently has more than 3 billion users and the support of more than 24,000 vendors. "We've been following RISC-V for a very ... » read more

Multi-Die Integration
By Ed Sperling - 04 Jan, 2023 - Comments: 0

Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this ... » read more

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2023 - Comments: 0

Siemens EDA's Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers. Synopsys' Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity. Cadence's Paul McLellan ... » read more

Startup Funding: December 2022
By Jesse Allen - 04 Jan, 2023 - Comments: 0

The month of December saw six rounds of $100 million or more. The largest, at a massive half-billion dollars, will support manufacturing of 12-inch monocrystalline silicon polished wafers and epitaxial wafers in China. The company is aiming for a production rate of 1 million pieces a month when current expansion is completed. Also in the half-billion club last month is a company making auton... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 22 Dec, 2022 - Comments: 0

RISC-V The European Union said it will spend the equivalent of $286.5 million on a high performance computing ecosystem based on RISC-V. According to the call for proposals, the aim of the project is to “establish a partnership between the EuroHPC JU and a consortium of industry, research organizations and institutions in HPC to the development of innovative HPC hardware and software technol... » read more

Comprehensive S-Parameter Verification Coverage With Analog FastSPICE
By Siemens EDA - 22 Dec, 2022 - Comments: 0

IC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies, multi-die chips, stacked 3D ICs and advanced packaging. Furthermore, design technology continues to progress towards supporting higher data rates to address the increasing demand for more and enhanced connectivity. We now must deal with much more... » read more

Readership Explosion
By Brian Bailey - 21 Dec, 2022 - Comments: 0

Every year, I use my last blog of the year to look back over the stories that have been published in the Systems and Design and Low Power-High Performance channels — the two channels that I write for — at Semiconductor Engineering. I am looking for the most read stories. I do this for a number of reasons, such as trying to gauge if readers' interests are changing, and the preferred type and... » read more

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