category: Architectures

category: IoT, Security & Automotive

HBM-Enabled FPGA-Based Graph Processing Accelerator
By Technical Paper Link - 19 Feb, 2023 - Comments: 0

A technical paper titled "ACTS: A Near-Memory FPGA Graph Processing Framework" was published by researchers at University of Virginia and Samsung. Abstract: "Despite the high off-chip bandwidth and on-chip parallelism offered by today's near-memory accelerators, software-based (CPU and GPU) graph processing frameworks still suffer performance degradation from under-utilization of available ... » read more

Review of Tools & Techniques for DL Edge Inference
By Technical Paper Link - 16 Feb, 2023 - Comments: 0

A new technical paper titled "Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review" was published in "Proceedings of the IEEE" by researchers at University of Missouri and Texas Tech University. Abstract: Successful integration of deep neural networks (DNNs) or deep learning (DL) has resulted in breakthroughs in many areas. However, deploying thes... » read more

Emulation System for Racetrack Memories Based on FPGA
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "ERMES: Efficient Racetrack Memory Emulation System based on FPGA" was written by researchers at University of Calabria and TU Dresden. "This paper presents a new emulation system for RTMs based on heterogeneous FPGA-CPU Systems-on-Chips (SoCs). Thanks to its high flexibility, the proposed emulator can be easily configured to evaluate different memory architectures. ... » read more

Hardware Virtualization Support in the RISC-V CVA6 Core
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration" was written by researchers at Universidade do Minho (Portugal), University of Bologna, and ETH Zurich. Abstract Excerpt: "In this article, we describe our work on hardware virtualization support in the RISC-V CVA6 core. Our contribution is multifold and encompasses archite... » read more

Transferring Qubits Directly Between Quantum Computing Microchips (U. of Sussex/ Universal Quantum)
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "A high-fidelity quantum matter-link between ion-trap microchip modules" was published by researchers at University of Sussex, Universal Quantum Ltd, University College London and University of Bristol. “As quantum computers grow, we will eventually be constrained by the size of the microchip, which limits the number of quantum bits such a chip can accommodate.... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Automotive E/E Architectures with Safety Related Availability (SaRa) Requirements For Highly Autonomous Driving
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Multi-objective optimization for safety-related available E/E architectures scoping highly automated driving vehicles" was written by researchers at Robert Bosch GmBbH and University of Luxembourg. Abstract: "Megatrends such as Highly Automated Driving (HAD) (SAE ≥ Level-3), electrification, and connectivity are reshaping the automotive industry. Together with th... » read more

Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Failure Tolerant Training with Persistent Memory Disaggregation over CXL" was published (preprint) by researchers at KAIST and Panmnesia. "TRAININGCXL can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead," states the paper. Find the technical paper here. or here (IEE... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)
By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

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