Impact of Semiconductor Optical Amplifers On Performance & Power Consumption in Data Centers (UCSB)


A new technical paper titled "Integrated SOAs enable energy-efficient intra-data center coherent links" was published by researchers at UC Santa Barbara. "In this work, we analyze the impact of integrated semiconductor optical amplifiers (SOAs) on link performance and power consumption, and describe the optimal design spaces for low-cost and energy-efficient coherent links. Placing SOAs afte... » read more

Memory Disaggregation Research And Making It Practical With Hardware Trends (U. of Michigan)


A new technical paper titled "Memory Disaggregation: Advances and Open Challenges" was published by researchers at University of Michigan. Abstract "Compute and memory are tightly coupled within each server in traditional datacenters. Large-scale datacenter operators have identified this coupling as a root cause behind fleet-wide resource underutilization and increasing Total Cost of Owners... » read more

Edge HW-SW Co-Design Platform Integrating RISC-V And HW Accelerators


A new technical paper titled "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators" was published by researchers at Columbia University. "We introduce a hardware/software co-design approach that combines software applications designed with Eigen, a powerful open-source C++ library that abstracts linear-algebra workloads, and real-time execution on heterog... » read more

Server Design With Pin-Efficient CXL Interface (Georgia Tech)


A new technical paper titled "A Case for CXL-Centric Server Processors" was written by researchers at Georgia Tech. Abstract: "The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands, DDR--the dominant processor inter... » read more

Performance Of Analog In-Memory Computing On Imaging Problems


A technical paper titled "Accelerating AI Using Next-Generation Hardware: Possibilities and Challenges With Analog In-Memory Computing" was published by researchers at Lund University and Ericsson Research. Abstract "Future generations of computing systems need to continue increasing processing speed and energy efficiency in order to meet the growing workload requirements under stringent en... » read more

28nm-HKMG-Based FeFET Devices For Synaptic Applications


A technical paper titled "28 nm high-k-metal gate ferroelectric field effect transistors based synapses- A comprehensive overview" was published by researchers at Fraunhofer-Institut für Photonische Mikrosysteme IPMS, Indian Institute of Technology Madras, and GlobalFoundries. Abstract This invited article we present a comprehensive overview of 28 nm high-k-metal gate-based ferroelectric f... » read more

Recent Developments in Neuromorphic Computing, Focusing on Hardware Design and Reliability


A new technical paper titled "Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies" was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino. Abstract "The field of neuromorphic computing has been rapidly evolving in recent years, with an incre... » read more

Toolbox For Designing Heterogeneous Quantum Systems


A new technical paper titled "Microarchitectures for Heterogeneous Superconducting Quantum Computers" was published by researcher at: Pacific Northwest National Laboratory, Princeton University, University of Chicago, Rutgers University, MIT, Brookhaven National Laboratory, and Infleqtion. Abstract: "Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, ... » read more

EPFL’s Open Source Single-Core RISC-V Microcontroller for Edge Computing


A new technical paper titled "X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller" was published by researchers at Ecole Polytechnique Fédérale de Lausanne (EPFL). Abstract: "In this work, we present eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP), a configurable and extendible single-core RISC-V-based ultra-low-power microcontroller. X-HEEP can be used ... » read more

RISC-V Vectorization And Potential for HPC


A new technical paper titled "Test-driving RISC-V Vector hardware for HPC" was published by researchers at University of Edinburgh. Abstract: "Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V. This is important because vectorisation is crucial to obt... » read more

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