CXL-Based Memory Pooling System Meets Cloud Performance Goals And Significantly Reduces DRAM Cost


A technical paper titled "Pond: CXL-Based Memory Pooling Systems for Cloud Platforms" was published by researchers at Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. Abstract "Public cloud providers seek to meet stringent performance requirements and low hardware cost. A key driver of performance and cost is main memory. Memory pooling promises to improve DRAM utilization and t... » read more

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)


A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

Flexible In-Field Test of a CAN Controller


A technical paper titled "A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers" was published by Delft University of Technology, Cadence, and Politecnico di Torino. Abstract "In order to match the strict reliability requirements mandated by regulations and standards adopted in the automotive sector, as well as other domains where safety is a major conc... » read more

Multi-Wavelength, Multimode Communication Scheme For On-Chip and Chip-to-Chip Interconnects


A technical paper titled "Multi-dimensional data transmission using inverse-designed silicon photonics and microcombs" was published by researchers at Stanford, Harvard, University of Central Florida, NIST, and others. "Here we demonstrate an integrated multi-dimensional communication scheme that combines wavelength- and mode- multiplexing on a silicon photonic circuit. Using foundry-compati... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)


A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Chip Sandwich: Electronics Chip & Photonics Chip Co-Optimized To Work Together (CalTech/Univ. of Southampton)


A technical paper titled "A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators" was published by researchers at CalTech and University of Southampton. "The resulting optimized interface between the two chips allows them to transmit 100 gigabits of data per second while producing just 2.4 pico-Joules per transmitted bit. This improves th... » read more

3-to-1 Reconfigurable Analog Signal Modulation Circuit On A Single Device


A new technical paper titled "Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor" was published by researchers at NaMLab gGmbH, GlobalFoundries, and TU Dresden. "Reconfigurable field effect transistors are an emerging class of electronic devices, which exploit a structure with multiple independent gates to selectively adjust the charge carrier ... » read more

Hardware Trojan Inserted Inside A RISC-V Based Automotive Telematics Control Unit


A new technical paper titled "On the Feasibility of Remotely Triggered Automotive Hardware Trojans" was written by researchers at Georgia Tech. "In this paper, we discuss how Hardware Trojans can act as the physical access intermediates to allow the remote triggering of malicious payloads embedded in ECUs, through seemingly benign wireless communication. We demonstrate a proof of concept ECU... » read more

Locking-Based Design-For-Security Methodology To Prevent Piracy of RF transceiver ICs


A new technical paper titled "Anti-Piracy Design of RF Transceivers" was published by researchers at Sorbonne Universite (France). Abstract: "We present a locking-based design-for-security methodology to prevent piracy of RF transceiver integrated circuits. The solution is called SyncLock as it locks the synchronization of the transmitter with the receiver. If a key other than the secret ... » read more

More Efficient On-Chip Laser Frequency Comb (Harvard)


A new technical paper titled "High-efficiency and broadband on-chip electro-optic frequency comb generators" was published by researchers at Harvard, Stanford, Caltech, and Hyperlight. The research claims the electro-optic frequency device is 100% more efficient and has 2X the bandwidth of previous technology.    According to Harvard's news release, "the latest research applies the two con... » read more

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