category: Design & Verification

category: IoT, Security & Automotive

Hardware Fuzzing (U. of Michigan, Google, Virginia Tech)
By Technical Paper Link - 18 Dec, 2022 - Comments: 0

A technical paper titled "Fuzzing Hardware Like Software" was published by researchers at University of Michigan, Google and Virginia Tech. The paper was presented at the 2022 Usenix Security Symposium. Abstract: "Hardware flaws are permanent and potent: hardware cannot be patched once fabricated, and any flaws may undermine even formally verified software executing on top. Consequently, ve... » read more

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies" was published by researchers at UT Austin and NVIDIA. "This paper presents AutoCRAFT, an automatic layout generator targeting region-based layouts for advanced FinFET-based full-custom circuits. AutoCRAFT uses specialized place-and-route (P&R) algorithms to handle various design cons... » read more

Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)
By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

Hardware Security: New Mathematical Model To Quantify Information Flow in Digital Circuits For Different Attack Models (RWTH Aachen)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A new technical paper titled "Quantitative Information Flow for Hardware: Advancing the Attack Landscape" was published by researchers at RWTH Aachen University. Abstract: "Security still remains an afterthought in modern Electronic Design Automation (EDA) tools, which solely focus on enhancing performance and reducing the chip size. Typically, the security analysis is conducted by hand, l... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

HW Security: Fingerprints Of Digital Circuits Using Electromagnetic Side-Channel Sensing & Simulations (Georgia Tech)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Circuit Activity Fingerprinting Using Electromagnetic Side-Channel Sensing and Digital Circuit Simulations" was published by researchers at Georgia Tech. The work "introduces a novel circuit identification method based on “fingerprints” of periodic circuit activity that does not rely on any circuit-specific reference measurements. We capture these “fingerprint... » read more

Using Sparseloop in Hardware Accelerator Design Flows (MIT)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling" was published by researchers at MIT and NVIDIA.  The paper won "Distinguished Artifact Award" at the MICRO 2022 conference. Find the technical paper here.  Published 2022.  Project website is here and github here. Abstract: "In recent years, many accelerators have been proposed to effici... » read more

Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

Lithography Modeling: Data Augmentation Framework
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design" was published by researchers at the University of Texas at Austin, Nvidia, and the California Institute of Technology. Abstract: "Lithography modeling is a crucial problem in chip design to ensure a chip design mask is manufacturable. It requires rigorous simulation... » read more

Memory and Energy-Efficient Batch Normalization Hardware
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training" was published by researchers at DGIST (Daegu Gyeongbuk Institute of Science and Technology). The work was supported by Samsung Research Funding Incubation Center. Abstract: "When training early-stage deep neural networks (DNNs), generating intermediate features via con... » read more

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