category: Memory

category: IoT, Security & Automotive

State of the Art And Future Directions of Rowhammer (ETH Zurich)
By Technical Paper Link - 18 Apr, 2023 - Comments: 0

A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon in... » read more

Spiking Neural Networks: Hardware & Algorithm Developments
By Technical Paper Link - 18 Apr, 2023 - Comments: 0

A new technical paper titled "Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware" was published by researchers at Purdue University, Pennsylvania State University, and Yale University. Excerpt from Abstract: "In this article, we outline several strides that neuromorphic computing based on spiking neural networks (SNNs) has taken over the recent past, a... » read more

SW-HW Framework: Graphic Rendering on RISC-V GPUs (Georgia Tech, Cal Poly)
By Technical Paper Link - 18 Apr, 2023 - Comments: 0

A new technical paper titled "Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs" was published by researchers at Georgia Tech, California Polytechnic State University-San Luis Obispo. Abstract Excerpt: "In this work, we present Skybox, a full-stack open-source GPU architecture with integrated software, compiler, hardware, and simulation environment, that enables end-to-end G... » read more

Automated Tool Flow From Domain-Specific Languages To Generate Massively Parallel Accelerators on HBM-Equipped FPGAs
By Technical Paper Link - 12 Apr, 2023 - Comments: 0

A new technical paper titled "Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics" was published by researchers at Politecnico di Milano and TU Dresden. The paper states "In this article, we propose an automated tool flow from a domain-specific language for tensor expressions to generate massively parallel acceler... » read more

Hybrid Hardware Fuzzer, Combining Capabilities of Formal Verification Methods And Fuzzing Tools
By Technical Paper Link - 11 Apr, 2023 - Comments: 0

A new technical paper titled "HyPFuzz: Formal-Assisted Processor Fuzzing" was published by researchers at Texas A&M University and Technische Universität Darmstadt. Abstract: "Recent research has shown that hardware fuzzers can effectively detect security vulnerabilities in modern processors. However, existing hardware fuzzers do not fuzz well the hard-to-reach design spaces. Consequently,... » read more

Digital Neuromorphic Processor: Algorithm-HW Co-design (imec / KU Leuven)
By Technical Paper Link - 11 Apr, 2023 - Comments: 0

A technical paper titled "Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design" was published by researchers at imec and KU Leuven. "In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architect... » read more

Scalable, Shared-L1-Memory Manycore RISC-V System
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory" was published by researchers at ETH Zurich and University of Bologna. Abstract: "Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly... » read more

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures" was published by researchers at National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente. Abstract "Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Tow... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Google’s TPU v4 Architecture: 3 Major Features
By Technical Paper Link - 07 Apr, 2023 - Comments: 0

A new technical paper titled "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings" was published by researchers at Google. Abstract: "In response to innovations in machine learning (ML) models, production workloads changed radically and rapidly. TPU v4 is the fifth Google domain specific architecture (DSA) and its third supercomputer f... » read more

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