category: Packaging

category: IoT, Security & Automotive

Artificial intelligence deep learning for 3D IC reliability prediction
By Technical Paper Link - 25 Apr, 2022 - Comments: 0

New research from National Yang Ming Chiao Tung University, National Center for High-Performance Computing (Taiwan), Tunghai University, MA-Tek Inc, and UCLA. Abstract "Three-dimensional integrated circuit (3D IC) technologies have been receiving much attention recently due to the near-ending of Moore’s law of minimization in 2D IC. However, the reliability of 3D IC, which is greatly infl... » read more

Investigation of integrated factors in the occurrence of copper wire bonding corrosion of semiconductor packages
By Technical Paper Link - 01 Apr, 2022 - Comments: 0

Abstract "Copper wire bonding has got attracted attention over gold wire bonding due to its lower cost. However, despite many unique aspects and properties of copper wire bonding, corrosion of copper wire bonding has become a point of interest as it leads to the failure of semiconductor packages. Current and future trends and development in miniaturization and multifunction of the semico... » read more

Designing a 2048-Chiplet, 14336-Core Waferscale Processor
By Technical Paper Link - 14 Mar, 2022 - Comments: 0

Abstract "Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant perfor... » read more

Warpage Of Compression Molded SiP Strips
By JCET - 17 Feb, 2022 - Comments: 0

By Eric Ouyang, Yonghyuk Jeong, JaeMyong Kim, JaePil Kim, OhYoung Kwon, and Michael Liu of JCET; and Susan Lin, Jenn An Wang, Anthony Yang, and Eric Yang of CoreTech System (Moldex3D). Abstract System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing p... » read more

Topology for Substrate Routing in Semiconductor Package Design
By Technical Paper Link - 15 Feb, 2022 - Comments: 0

Abstract: In this work, we propose a new signal routing method for solving routing problems that occur in the design process of semiconductor package substrates. Our work uses a topological transformation of the layers of the package substrate in order to simplify the routing problem into a problem of connecting points on a circle with non-intersecting straight line segments. The circle, whi... » read more

Impact Modifiers and Compatibilizers for Versatile Epoxy-Based Adhesive Films with Curing and Deoxidizing Capabilities
By Technical Paper Link - 04 Feb, 2022 - Comments: 0

Abstract: "Epoxy resins with acidic compounds feature adhesion, robustness, and deoxidizing ability. In this study, hybrid adhesive films with deoxidizing and curing capabilities for semiconductor packaging were fabricated. The compatibilizing effects and mechanical properties were chiefly investigated by using various additive binders (thermoplastic amorphous polymers) and compatibilizing a... » read more

X-ray Imaging of Silicon Die Within Fully Packaged Semiconductor Devices
By Technical Paper Link - 21 Jan, 2022 - Comments: 0

Abstract: "X-ray diffraction imaging (XRDI) (topography) measurements of silicon die warpage within fully packaged commercial quad-flat no-lead devices are described. Using synchrotron radiation, it has been shown that the tilt of the lattice planes in the Analog Devices AD9253 die initially falls, but after 100 °C, it rises again. The twist across the die wafer falls linearly with an incre... » read more

Conceptualized Improvement on Transparent Glass Die for a Robust Manufacturing Process
By Technical Paper Link - 17 Jan, 2022 - Comments: 0

Abstract: "Glass die are one of the materials used by semiconductor plants during production of specialized quad-flat no-leads (QFN) products. With its transparent appearance and fragile characteristics, several challenges are encountered and analyzed to resolve unwanted issues and to have a robust process manufacturing. This paper will discuss a potential concept of process improvement on t... » read more

TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "Heterogeneous systems are commonly used today to sustain the historic benefits we have achieved through technology scaling. 2.5D integration technology provides a cost-effective solution for designing heterogeneous systems. The traditional physical design of a 2.5D heterogeneous system closely packs the chiplets to minimize wirelength, but this leads to a thermally-inefficient design... » read more

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and sol... » read more

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