SB MOSFET-Based Ultra-Low Power Real-Time Neurons for Neuromorphic Computing (Indian Institute of Technology)


A technical paper titled “Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing” was published by researchers at the Indian Institute of Technology (IIT) Bombay. Abstract: "Energy-efficient real-time synapses and neurons are essential to enable large-scale neuromorphic computing. In this paper, we propose and demonstrate the Schottky-Barrier MOSFE... » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators


A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization


A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator


A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

A Step Towards Eliminating The Von-Neumann Bottleneck By Co-locating Photonic Computing Elements And Non-Volatile Memory 


A technical paper titled “Non-volatile heterogeneous III-V/Si photonics via optical charge-trap memory” was published by researchers at Hewlett Packard Enterprise. "We demonstrate, for the first time, non-volatile charge-trap flash memory (CTM) co-located with heterogeneous III-V/Si photonics. The wafer-bonded III-V/Si CTM cell facilitates non-volatile optical functionality for a variety... » read more

Object Detection CNN Suitable For Edge Processors With Limited Memory


A technical paper titled “TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers” was published by researchers at ETH Zurich. Abstract: "This paper introduces a highly flexible, quantized, memory-efficient, and ultra-lightweight object detection network, called TinyissimoYOLO. It aims to enable object detection on microcontrol... » read more

Advantages, Disadvantages, And Use Cases Of FPGAs


A technical paper titled “Data Processing with FPGAs on Modern Architectures” was published by researchers at ETH Zürich. Abstract: "Trends in hardware, the prevalence of the cloud, and the rise of highly demanding applications have ushered an era of specialization that is quickly changing the way data is processed at scale. These changes are likely to continue and accelerate in the next... » read more

Extreme Fast Charging by Regulating Lithium-Ion Batteries’ Self-Generated Heat Via Active Thermal Switching


A technical paper titled “Extreme fast charging of commercial Li-ion batteries via combined thermal switching and self-heating approaches” was published by researchers at Lawrence Berkeley National Laboratory, the University of California, Berkeley, and the Hong Kong University of Science and Technology. Abstract: "The mass adoption of electric vehicles is hindered by the inadequate ext... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact


A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

High Performance, Energy-Dense, Practical, And Reliable Solid-State Batteries (ORNL)


A technical paper titled “Tailoring of the Anti-Perovskite Solid Electrolytes at the Grain-Scale” was published by researchers at Oak Ridge National Laboratory. Abstract: "The development of thin, dense, defect-free solid electrolyte films is key for achieving practical and commercially viable solid-state batteries. Herein, we showcase a facile processing pathway for antiperovskite (Li2OH... » read more

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