category: Top Stories

category: IoT, Security & Automotive

Shrink Or Package?
By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Chip Test Shifts Left
By Jeff Dorsch - 07 Jun, 2017 - Comments: 0

“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

Security Issues Up With Heterogeneity
By Ann Mutschler - 05 Jun, 2017 - Comments: 0

The race toward heterogeneous designs is raising new security concerns across the semiconductor supply chain. There is more IP to track, more potential for unexpected interactions, and many more ways to steal data or IP. Security is a difficult problem no matter what kind of chip is involved, and it has been getting worse as more devices, machines and systems are connected to the Internet. B... » read more

What’s Next In Scaling, Stacking
By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

Testing IoT Devices
By Jeff Dorsch - 05 Jun, 2017 - Comments: 3

Internet of Things devices present new challenges in testing. Some devices can be tested the same way as standard semiconductors are now tested, but others call for different approaches. Microcontrollers and other chips that go into safety-critical applications — medical devices, military/aerospace systems, and automotive electronics — need their own kind of testing to make sure they wil... » read more

Wireless Test: Too Many Protocols
By Jeff Dorsch - 08 May, 2017 - Comments: 0

Testing wireless communications is getting far more difficult as more markets begin adding wireless communications and standards groups push to improve the speed, power and security of existing protocols. There is already a long list of protocols, and it's growing further as new communications technologies are added into the mix. With the addition of 5G, the new 802.11ax standard, and other ... » read more

Wirebond Technology Rolls On
By Mark LaPedus - 08 May, 2017 - Comments: 2

Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types. Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto... » read more

Intel Inside The Package
By Ed Sperling - 08 May, 2017 - Comments: 1

Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

Time For Massively Parallel Testing
By Jeff Dorsch - 12 Apr, 2017 - Comments: 0

Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory devices and other semiconductors, test equipment vendors have resorted to parallel testing technology, simultaneously testing multiple chips at a time. The industry also is turning to system-level tes... » read more

2.5D, FO-WLP Issues Come Into Focus
By Ann Mutschler - 10 Apr, 2017 - Comments: 2

Advanced packaging is beginning to take off after years of hype, spurred by 2.5D implementations in high-performance markets and fan-out wafer-level packaging for a wide array of applications. There are now more players viewing packaging as another frontier driving innovation. But perhaps a more telling sign is that large foundries in Taiwan have begun offering packaging services to customer... » read more

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